Commit fd18f00d authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'blackfin-for-linus' of... 

Merge tag 'blackfin-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/realmz6/blackfin-linux

Pull blackfin updates from Steven Miao:
 "Code cleanup, some previously ignored patches, and bug fixes"

* tag 'blackfin-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/realmz6/blackfin-linux:
  blackfin: cleanup board files
  bf609: clock: drop unused clock bit set/clear functions
  Blackfin: bf537: rename "CONFIG_ADT75"
  Blackfin: bf537: rename "CONFIG_AD7314"
  Blackfin: bf537: rename ad2s120x ->ad2s1200
  blackfin: bf537: fix typo "CONFIG_SND_SOC_ADV80X_MODULE"
  blackfin: dma: current count mmr is read only
  bfin_crc: Move architecture independant crc header file out of the blackfin folder.
  bf54x: drop unuesd HOST status,control,timeout registers bit define macros
  blackfin: portmux: cleanup head file
  Blackfin: remove "config IP_CHECKSUM_L1"
  blackfin: Remove GENERIC_GPIO config option again
  blackfin:Use generic /proc/interrupts implementation
  blackfin: bf60x: fix typo "CONFIG_PM_BFIN_WAKE_PA15_POL"
parents de0c9cf9 c4a2c58d

arch/blackfin/Kconfig

+1 −11
Original line number Diff line number Diff line
@@ -34,6 +34,7 @@ config BLACKFIN 
	select ARCH_WANT_IPC_PARSE_VERSION

	select GENERIC_ATOMIC64

	select GENERIC_IRQ_PROBE

	select GENERIC_IRQ_SHOW

	select HAVE_NMI_WATCHDOG if NMI_WATCHDOG

	select GENERIC_SMP_IDLE_THREAD

	select ARCH_USES_GETTIMEOFFSET if !GENERIC_CLOCKEVENTS
@@ -51,9 +52,6 @@ config GENERIC_BUG 
config ZONE_DMA

	def_bool y



config GENERIC_GPIO

	def_bool y



config FORCE_MAX_ZONEORDER

	int

	default "14"
@@ -870,14 +868,6 @@ config SYS_BFIN_SPINLOCK_L1 
	  If enabled, sys_bfin_spinlock function is linked

	  into L1 instruction memory. (less latency)



config IP_CHECKSUM_L1

	bool "Locate IP Checksum function in L1 Memory"

	default n

	depends on !SMP

	help

	  If enabled, the IP Checksum function is linked

	  into L1 instruction memory. (less latency)



config CACHELINE_ALIGNED_L1

	bool "Locate cacheline_aligned data to L1 Data Memory"

	default y if !BF54x

arch/blackfin/include/asm/bfin_crc.h

deleted100644 → 0
+0 −125
Original line number Diff line number Diff line 
/*

 * bfin_crc.h - interface to Blackfin CRC controllers

 *

 * Copyright 2012 Analog Devices Inc.

 *

 * Licensed under the GPL-2 or later.

 */



#ifndef __BFIN_CRC_H__

#define __BFIN_CRC_H__



/* Function driver which use hardware crc must initialize the structure */

struct crc_info {

	/* Input data address */

	unsigned char *in_addr;

	/* Output data address */

	unsigned char *out_addr;

	/* Input or output bytes */

	unsigned long datasize;

	union {

	/* CRC to compare with that of input buffer */

	unsigned long crc_compare;

	/* Value to compare with input data */

	unsigned long val_verify;

	/* Value to fill */

	unsigned long val_fill;

	};

	/* Value to program the 32b CRC Polynomial */

	unsigned long crc_poly;

	union {

	/* CRC calculated from the input data */

	unsigned long crc_result;

	/* First failed position to verify input data */

	unsigned long pos_verify;

	};

	/* CRC mirror flags */

	unsigned int bitmirr:1;

	unsigned int bytmirr:1;

	unsigned int w16swp:1;

	unsigned int fdsel:1;

	unsigned int rsltmirr:1;

	unsigned int polymirr:1;

	unsigned int cmpmirr:1;

};



/* Userspace interface */

#define CRC_IOC_MAGIC		'C'

#define CRC_IOC_CALC_CRC	_IOWR('C', 0x01, unsigned int)

#define CRC_IOC_MEMCPY_CRC	_IOWR('C', 0x02, unsigned int)

#define CRC_IOC_VERIFY_VAL	_IOWR('C', 0x03, unsigned int)

#define CRC_IOC_FILL_VAL	_IOWR('C', 0x04, unsigned int)





#ifdef __KERNEL__



#include <linux/types.h>

#include <linux/spinlock.h>

#include <linux/miscdevice.h>



struct crc_register {

	u32 control;

	u32 datacnt;

	u32 datacntrld;

	u32 __pad_1[2];

	u32 compare;

	u32 fillval;

	u32 datafifo;

	u32 intren;

	u32 intrenset;

	u32 intrenclr;

	u32 poly;

	u32 __pad_2[4];

	u32 status;

	u32 datacntcap;

	u32 __pad_3;

	u32 result;

	u32 curresult;

	u32 __pad_4[3];

	u32 revid;

};



/* CRC_STATUS Masks */

#define CMPERR			0x00000002	/* Compare error */

#define DCNTEXP			0x00000010	/* datacnt register expired */

#define IBR			0x00010000	/* Input buffer ready */

#define OBR			0x00020000	/* Output buffer ready */

#define IRR			0x00040000	/* Immediate result readt */

#define LUTDONE			0x00080000	/* Look-up table generation done */

#define FSTAT			0x00700000	/* FIFO status */

#define MAX_FIFO		4		/* Max fifo size */



/* CRC_CONTROL Masks */

#define BLKEN			0x00000001	/* Block enable */

#define OPMODE			0x000000F0	/* Operation mode */

#define OPMODE_OFFSET		4		/* Operation mode mask offset*/

#define MODE_DMACPY_CRC		1		/* MTM CRC compute and compare */

#define MODE_DATA_FILL		2		/* MTM data fill */

#define MODE_CALC_CRC		3		/* MSM CRC compute and compare */

#define MODE_DATA_VERIFY	4		/* MSM data verify */

#define AUTOCLRZ		0x00000100	/* Auto clear to zero */

#define AUTOCLRF		0x00000200	/* Auto clear to one */

#define OBRSTALL		0x00001000	/* Stall on output buffer ready */

#define IRRSTALL		0x00002000	/* Stall on immediate result ready */

#define BITMIRR			0x00010000	/* Mirror bits within each byte of 32-bit input data */

#define BITMIRR_OFFSET		16		/* Mirror bits offset */

#define BYTMIRR			0x00020000	/* Mirror bytes of 32-bit input data */

#define BYTMIRR_OFFSET		17		/* Mirror bytes offset */

#define W16SWP			0x00040000	/* Mirror uppper and lower 16-bit word of 32-bit input data */

#define W16SWP_OFFSET		18		/* Mirror 16-bit word offset */

#define FDSEL			0x00080000	/* FIFO is written after input data is mirrored */

#define FDSEL_OFFSET		19		/* Mirror FIFO offset */

#define RSLTMIRR		0x00100000	/* CRC result registers are mirrored. */

#define RSLTMIRR_OFFSET		20		/* Mirror CRC result offset. */

#define POLYMIRR		0x00200000	/* CRC poly register is mirrored. */

#define POLYMIRR_OFFSET		21		/* Mirror CRC poly offset. */

#define CMPMIRR			0x00400000	/* CRC compare register is mirrored. */

#define CMPMIRR_OFFSET		22		/* Mirror CRC compare offset. */



/* CRC_INTREN Masks */

#define CMPERRI 		0x02		/* CRC_ERROR_INTR */

#define DCNTEXPI 		0x10		/* CRC_STATUS_INTR */



#endif



#endif

arch/blackfin/include/asm/dma.h

+0 −2
Original line number Diff line number Diff line
@@ -316,8 +316,6 @@ static inline void disable_dma(unsigned int channel) 
}

static inline void enable_dma(unsigned int channel)

{

	dma_ch[channel].regs->curr_x_count = 0;

	dma_ch[channel].regs->curr_y_count = 0;

	dma_ch[channel].regs->cfg |= DMAEN;

}

int set_dma_callback(unsigned int channel, irq_handler_t callback, void *data);

arch/blackfin/include/asm/portmux.h

+4 −6
Original line number Diff line number Diff line
@@ -18,16 +18,14 @@ 
#define P_DONTCARE	0x1000



#ifdef CONFIG_PINCTRL

#include <asm/irq_handler.h>

int bfin_internal_set_wake(unsigned int irq, unsigned int state);



#define gpio_pint_regs bfin_pint_regs

#define adi_internal_set_wake bfin_internal_set_wake



#define peripheral_request(per, label) 0

#define peripheral_request(per, label) (0)

#define peripheral_free(per)

#define peripheral_request_list(per, label) \

	(pdev ? (IS_ERR(devm_pinctrl_get_select_default(&pdev->dev)) \

	? -EINVAL : 0) : 0)

#define peripheral_request_list(per, label) (0)

#define peripheral_free_list(per)

#else

int peripheral_request(unsigned short per, const char *label);
@@ -39,7 +37,7 @@ void peripheral_free_list(const unsigned short per[]); 
#include <linux/err.h>

#include <linux/pinctrl/pinctrl.h>

#include <mach/portmux.h>

#include <linux/gpio.h>

#include <mach/gpio.h>



#ifndef P_SPORT2_TFS

#define P_SPORT2_TFS P_UNDEF

arch/blackfin/kernel/irqchip.c

+9 −30
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ 
#include <linux/kallsyms.h>

#include <linux/interrupt.h>

#include <linux/irq.h>

#include <linux/seq_file.h>

#include <asm/irq_handler.h>

#include <asm/trace.h>

#include <asm/pda.h>
@@ -33,37 +34,15 @@ static struct irq_desc bad_irq_desc = { 
#endif



#ifdef CONFIG_PROC_FS

int show_interrupts(struct seq_file *p, void *v)

int arch_show_interrupts(struct seq_file *p, int prec)

{

	int i = *(loff_t *) v, j;

	struct irqaction *action;

	unsigned long flags;



	if (i < NR_IRQS) {

		struct irq_desc *desc = irq_to_desc(i);



		raw_spin_lock_irqsave(&desc->lock, flags);

		action = desc->action;

		if (!action)

			goto skip;

		seq_printf(p, "%3d: ", i);

		for_each_online_cpu(j)

			seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));

		seq_printf(p, " %8s", irq_desc_get_chip(desc)->name);

		seq_printf(p, "  %s", action->name);

		for (action = action->next; action; action = action->next)

			seq_printf(p, "  %s", action->name);



		seq_putc(p, '\n');

 skip:

		raw_spin_unlock_irqrestore(&desc->lock, flags);

	} else if (i == NR_IRQS) {

		seq_printf(p, "NMI: ");

	int j;



	seq_printf(p, "%*s: ", prec, "NMI");

	for_each_online_cpu(j)

		seq_printf(p, "%10u ", cpu_pda[j].__nmi_count);

	seq_printf(p, "  CORE  Non Maskable Interrupt\n");

		seq_printf(p, "Err: %10u\n",  atomic_read(&irq_err_count));

	}

	seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));

	return 0;

}

#endif

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