Commit fcfdfe30 authored by Will Deacon's avatar Will Deacon Committed by Ingo Molnar
Browse files

locking/barriers: Introduce smp_cond_load_relaxed() and atomic_cond_read_relaxed() 



Whilst we currently provide smp_cond_load_acquire() and
atomic_cond_read_acquire(), there are cases where the ACQUIRE semantics are
not required because of a subsequent fence or release operation once the
conditional loop has exited.

This patch adds relaxed versions of the conditional spinning primitives
to avoid unnecessary barrier overhead on architectures such as arm64.

Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
Acked-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Acked-by: default avatarWaiman Long <longman@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: boqun.feng@gmail.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: paulmck@linux.vnet.ibm.com
Link: http://lkml.kernel.org/r/1524738868-31318-2-git-send-email-will.deacon@arm.com


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent 0644f186

include/asm-generic/atomic-long.h

+2 −0
Original line number Diff line number Diff line
@@ -244,6 +244,8 @@ static inline long atomic_long_add_unless(atomic_long_t *l, long a, long u) 
#define atomic_long_inc_not_zero(l) \

	ATOMIC_LONG_PFX(_inc_not_zero)((ATOMIC_LONG_PFX(_t) *)(l))



#define atomic_long_cond_read_relaxed(v, c) \

	ATOMIC_LONG_PFX(_cond_read_relaxed)((ATOMIC_LONG_PFX(_t) *)(v), (c))

#define atomic_long_cond_read_acquire(v, c) \

	ATOMIC_LONG_PFX(_cond_read_acquire)((ATOMIC_LONG_PFX(_t) *)(v), (c))

include/asm-generic/barrier.h

+21 −6
Original line number Diff line number Diff line
@@ -221,18 +221,17 @@ do { \ 
#endif



/**

 * smp_cond_load_acquire() - (Spin) wait for cond with ACQUIRE ordering

 * smp_cond_load_relaxed() - (Spin) wait for cond with no ordering guarantees

 * @ptr: pointer to the variable to wait on

 * @cond: boolean expression to wait for

 *

 * Equivalent to using smp_load_acquire() on the condition variable but employs

 * the control dependency of the wait to reduce the barrier on many platforms.

 * Equivalent to using READ_ONCE() on the condition variable.

 *

 * Due to C lacking lambda expressions we load the value of *ptr into a

 * pre-named variable @VAL to be used in @cond.

 */

#ifndef smp_cond_load_acquire

#define smp_cond_load_acquire(ptr, cond_expr) ({		\

#ifndef smp_cond_load_relaxed

#define smp_cond_load_relaxed(ptr, cond_expr) ({		\

	typeof(ptr) __PTR = (ptr);				\

	typeof(*ptr) VAL;					\

	for (;;) {						\
@@ -241,10 +240,26 @@ do { \ 
			break;					\

		cpu_relax();					\

	}							\

	smp_acquire__after_ctrl_dep();				\

	VAL;							\

})

#endif



/**

 * smp_cond_load_acquire() - (Spin) wait for cond with ACQUIRE ordering

 * @ptr: pointer to the variable to wait on

 * @cond: boolean expression to wait for

 *

 * Equivalent to using smp_load_acquire() on the condition variable but employs

 * the control dependency of the wait to reduce the barrier on many platforms.

 */

#ifndef smp_cond_load_acquire

#define smp_cond_load_acquire(ptr, cond_expr) ({		\

	typeof(*ptr) _val;					\

	_val = smp_cond_load_relaxed(ptr, cond_expr);		\

	smp_acquire__after_ctrl_dep();				\

	_val;							\

})

#endif



#endif /* !__ASSEMBLY__ */

#endif /* __ASM_GENERIC_BARRIER_H */

include/linux/atomic.h

+2 −0
Original line number Diff line number Diff line
@@ -654,6 +654,7 @@ static inline int atomic_dec_if_positive(atomic_t *v) 
}

#endif



#define atomic_cond_read_relaxed(v, c)	smp_cond_load_relaxed(&(v)->counter, (c))

#define atomic_cond_read_acquire(v, c)	smp_cond_load_acquire(&(v)->counter, (c))



#ifdef CONFIG_GENERIC_ATOMIC64
@@ -1075,6 +1076,7 @@ static inline long long atomic64_fetch_andnot_release(long long i, atomic64_t *v 
}

#endif



#define atomic64_cond_read_relaxed(v, c)	smp_cond_load_relaxed(&(v)->counter, (c))

#define atomic64_cond_read_acquire(v, c)	smp_cond_load_acquire(&(v)->counter, (c))



#include <asm-generic/atomic-long.h>

CRA Git | Maintained and supported by SUSTech CRA and CCSE