Commit fcee01b9 authored by Harry Wentland's avatar Harry Wentland Committed by Alex Deucher
Browse files

drm/amd/display: Add DCN2 clk mgr 



Adds support for handling of clocking relevant to the DCN2 block,
including programming of the DCCG (Display Controller Clock Generator)
block:

HW Blocks:

    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+

Signed-off-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ca4d9b3a

drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile

+12 −0
Original line number Diff line number Diff line
@@ -73,3 +73,15 @@ AMD_DAL_CLK_MGR_DCN10 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn10/,$(CLK_MGR_DC 


AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN10)

endif



ifdef CONFIG_DRM_AMD_DC_DCN2_0

###############################################################################

# DCN20

###############################################################################

CLK_MGR_DCN20 = dcn20_clk_mgr.o



AMD_DAL_CLK_MGR_DCN20 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn20/,$(CLK_MGR_DCN20))



AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN20)

endif

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

+7 −25
Original line number Diff line number Diff line
@@ -34,31 +34,7 @@ 
#include "dce120/dce120_clk_mgr.h"

#include "dcn10/rv1_clk_mgr.h"

#include "dcn10/rv2_clk_mgr.h"





int clk_mgr_helper_get_active_display_cnt(

		struct dc *dc,

		struct dc_state *context)

{

	int i, display_count;



	display_count = 0;

	for (i = 0; i < context->stream_count; i++) {

		const struct dc_stream_state *stream = context->streams[i];



		/*

		 * Only notify active stream or virtual stream.

		 * Need to notify virtual stream to work around

		 * headless case. HPD does not fire when system is in

		 * S0i2.

		 */

		if (!stream->dpms_off || stream->signal == SIGNAL_TYPE_VIRTUAL)

			display_count++;

	}



	return display_count;

}



#include "dcn20/dcn20_clk_mgr.h"



struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg)

{
@@ -117,6 +93,12 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p 
		break;

#endif	/* Family RV */



#if defined(CONFIG_DRM_AMD_DC_DCN2_0)

	case FAMILY_NV:

		dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

		break;

#endif /* Family NV */



	default:

		ASSERT(0); /* Unknown Asic */

		break;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h

+0 −22
Original line number Diff line number Diff line
@@ -29,28 +29,6 @@ 


#include "dc.h"



/* Starting DID for each range */

enum dentist_base_divider_id {

	DENTIST_BASE_DID_1 = 0x08,

	DENTIST_BASE_DID_2 = 0x40,

	DENTIST_BASE_DID_3 = 0x60,

	DENTIST_BASE_DID_4 = 0x7e,

	DENTIST_MAX_DID = 0x7f

};



/* Starting point and step size for each divider range.*/

enum dentist_divider_range {

	DENTIST_DIVIDER_RANGE_1_START = 8,   /* 2.00  */

	DENTIST_DIVIDER_RANGE_1_STEP  = 1,   /* 0.25  */

	DENTIST_DIVIDER_RANGE_2_START = 64,  /* 16.00 */

	DENTIST_DIVIDER_RANGE_2_STEP  = 2,   /* 0.50  */

	DENTIST_DIVIDER_RANGE_3_START = 128, /* 32.00 */

	DENTIST_DIVIDER_RANGE_3_STEP  = 4,   /* 1.00  */

	DENTIST_DIVIDER_RANGE_4_START = 248, /* 62.00 */

	DENTIST_DIVIDER_RANGE_4_STEP  = 264, /* 66.00 */

	DENTIST_DIVIDER_RANGE_SCALE_FACTOR = 4

};



/* functions shared by other dce clk mgrs */

int dce_adjust_dp_ref_freq_for_ss(struct clk_mgr_internal *clk_mgr_dce, int dp_ref_clk_khz);

int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

+24 −1
Original line number Diff line number Diff line
@@ -114,6 +114,29 @@ static void ramp_up_dispclk_with_dpp(struct clk_mgr_internal *clk_mgr, struct dc 
	clk_mgr->base.clks.max_supported_dppclk_khz = new_clocks->max_supported_dppclk_khz;

}



static int get_active_display_cnt(

		struct dc *dc,

		struct dc_state *context)

{

	int i, display_count;



	display_count = 0;

	for (i = 0; i < context->stream_count; i++) {

		const struct dc_stream_state *stream = context->streams[i];



		/*

		 * Only notify active stream or virtual stream.

		 * Need to notify virtual stream to work around

		 * headless case. HPD does not fire when system is in

		 * S0i2.

		 */

		if (!stream->dpms_off || stream->signal == SIGNAL_TYPE_VIRTUAL)

			display_count++;

	}



	return display_count;

}



static void rv1_update_clocks(struct clk_mgr *clk_mgr_base,

			struct dc_state *context,

			bool safe_to_lower)
@@ -133,7 +156,7 @@ static void rv1_update_clocks(struct clk_mgr *clk_mgr_base, 


	pp_smu = &clk_mgr->pp_smu->rv_funcs;



	display_count = clk_mgr_helper_get_active_display_cnt(dc, context);

	display_count = get_active_display_cnt(dc, context);



	if (display_count == 0)

		enter_display_off = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c

+28 −30
Original line number Diff line number Diff line
@@ -68,59 +68,57 @@ static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0, 0, 0, 0 } }, 
#define VBIOSSMC_MSG_SetDispclkFreq           0x4

#define VBIOSSMC_MSG_SetDprefclkFreq          0x5



int rv1_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, unsigned int msg_id, unsigned int param)

int rv1_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)

{



	int actual_dispclk_set_khz = -1;

	struct dc *core_dc = clk_mgr->base.ctx->dc;

	struct dmcu *dmcu = core_dc->res_pool->dmcu;



	/* First clear response register */

	//dm_write_reg(ctx, mmMP1_SMN_C2PMSG_91, 0);

	REG_WRITE(MP1_SMN_C2PMSG_91, 0);



	/* Set the parameter register for the SMU message, unit is Mhz */

	REG_WRITE(MP1_SMN_C2PMSG_83, param);

	//dm_write_reg(ctx, mmMP1_SMN_C2PMSG_83, requested_dispclk_khz / 1000);

	REG_WRITE(MP1_SMN_C2PMSG_83, requested_dispclk_khz / 1000);



	/* Trigger the message transaction by writing the message ID */

	REG_WRITE(MP1_SMN_C2PMSG_67, msg_id);

	//dm_write_reg(ctx, mmMP1_SMN_C2PMSG_67, VBIOSSMC_MSG_SetDispclkFreq);

	REG_WRITE(MP1_SMN_C2PMSG_67, VBIOSSMC_MSG_SetDispclkFreq);



	REG_WAIT(MP1_SMN_C2PMSG_91, CONTENT, 1, 10, 200000);



	/* Actual dispclk set is returned in the parameter register */

	return REG_READ(MP1_SMN_C2PMSG_83);

}



int rv1_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)

{

	int actual_dispclk_set_mhz = -1;

	struct dc *core_dc = clk_mgr->base.ctx->dc;

	struct dmcu *dmcu = core_dc->res_pool->dmcu;



	/*  Unit of SMU msg parameter is Mhz */

	actual_dispclk_set_mhz = rv1_vbios_smu_send_msg_with_param(

			clk_mgr,

			VBIOSSMC_MSG_SetDispclkFreq,

			requested_dispclk_khz / 1000);



	/* Actual dispclk set is returned in the parameter register */

	actual_dispclk_set_mhz = REG_READ(MP1_SMN_C2PMSG_83) * 1000;

	actual_dispclk_set_khz = REG_READ(MP1_SMN_C2PMSG_83) * 1000;



	if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {

		if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {

			if (clk_mgr->dfs_bypass_disp_clk != actual_dispclk_set_mhz)

			if (clk_mgr->dfs_bypass_disp_clk != actual_dispclk_set_khz)

				dmcu->funcs->set_psr_wait_loop(dmcu,

						actual_dispclk_set_mhz / 7);

						actual_dispclk_set_khz / 1000 / 7);

		}

	}



	return actual_dispclk_set_mhz * 1000;

	return actual_dispclk_set_khz;

}



int rv1_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr)

{

	int actual_dprefclk_set_mhz = -1;

	int actual_dprefclk_set_khz = -1;



	REG_WRITE(MP1_SMN_C2PMSG_91, 0);



	/* Set the parameter register for the SMU message */

	REG_WRITE(MP1_SMN_C2PMSG_83, clk_mgr->base.dprefclk_khz / 1000);



	actual_dprefclk_set_mhz = rv1_vbios_smu_send_msg_with_param(

			clk_mgr,

			VBIOSSMC_MSG_SetDprefclkFreq,

			clk_mgr->base.dprefclk_khz / 1000);

	/* Trigger the message transaction by writing the message ID */

	REG_WRITE(MP1_SMN_C2PMSG_67, VBIOSSMC_MSG_SetDprefclkFreq);



	/* Wait for SMU response */

	REG_WAIT(MP1_SMN_C2PMSG_91, CONTENT, 1, 10, 200000);



	/* TODO: add code for programing DP DTO, currently this is down by command table */

	actual_dprefclk_set_khz = REG_READ(MP1_SMN_C2PMSG_83) * 1000;



	return actual_dprefclk_set_mhz * 1000;

	return actual_dprefclk_set_khz;

}

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