Commit fcc6aa8f authored by Tejas Upadhyay's avatar Tejas Upadhyay Committed by José Roberto de Souza
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drm/i915/ehl: Implement W/A 22010492432 



As per W/A implemented for TGL to program half of the nominal
DCO divider fraction value which is also applicable on EHL.

Changes since V2:
	- Apply stepping B0 till FOREVER
	- B0 - revid update as per Bspec 29153
Changes since V1:
        - ehl_ used as to keep earliest platform prefix
        - WA required B0 stepping onwards

Cc: Deak Imre <imre.deak@intel.com>
Signed-off-by: default avatarTejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
Signed-off-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201104050655.171185-1-tejaskumarx.surendrakumar.upadhyay@intel.com
parent 66186acb

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

+8 −5
Original line number Diff line number Diff line
@@ -2636,13 +2636,16 @@ static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state) 
}



/*

 * Display WA #22010492432: tgl

 * Display WA #22010492432: ehl, tgl

 * Program half of the nominal DCO divider fraction value.

 */

static bool

tgl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)

ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)

{

	return IS_TIGERLAKE(i915) && i915->dpll.ref_clks.nssc == 38400;

	return ((IS_PLATFORM(i915, INTEL_ELKHARTLAKE) &&

		 IS_JSL_EHL_REVID(i915, EHL_REVID_B0, REVID_FOREVER)) ||

		 IS_TIGERLAKE(i915)) &&

		 i915->dpll.ref_clks.nssc == 38400;

}



static int __cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
@@ -2696,7 +2699,7 @@ static int __cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv, 
	dco_fraction = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>

		       DPLL_CFGCR0_DCO_FRACTION_SHIFT;



	if (tgl_combo_pll_div_frac_wa_needed(dev_priv))

	if (ehl_combo_pll_div_frac_wa_needed(dev_priv))

		dco_fraction *= 2;



	dco_freq += (dco_fraction * ref_clock) / 0x8000;
@@ -3086,7 +3089,7 @@ static void icl_calc_dpll_state(struct drm_i915_private *i915, 


	memset(pll_state, 0, sizeof(*pll_state));



	if (tgl_combo_pll_div_frac_wa_needed(i915))

	if (ehl_combo_pll_div_frac_wa_needed(i915))

		dco_fraction = DIV_ROUND_CLOSEST(dco_fraction, 2);



	pll_state->cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(dco_fraction) |

drivers/gpu/drm/i915/i915_drv.h

+1 −0
Original line number Diff line number Diff line
@@ -1559,6 +1559,7 @@ extern const struct i915_rev_steppings kbl_revids[]; 
	(IS_ICELAKE(p) && IS_REVID(p, since, until))



#define EHL_REVID_A0            0x0

#define EHL_REVID_B0            0x1



#define IS_JSL_EHL_REVID(p, since, until) \

	(IS_JSL_EHL(p) && IS_REVID(p, since, until))

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