Commit fca10378 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'x86-urgent-2020-02-22' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 fixes from Thomas Gleixner:
 "Two fixes for x86:

   - Remove the __force_oder definiton from the kaslr boot code as it is
     already defined in the page table code which makes GCC 10 builds
     fail because it changed the default to -fno-common.

   - Address the AMD erratum 1054 concerning the IRPERF capability and
     enable the Instructions Retired fixed counter on machines which are
     not affected by the erratum"

* tag 'x86-urgent-2020-02-22' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/cpu/amd: Enable the fixed Instructions Retired counter IRPERF
  x86/boot/compressed: Don't declare __force_order in kaslr_64.c
parents 0a115e5f 21b5ee59

arch/x86/boot/compressed/kaslr_64.c

+0 −3
Original line number Diff line number Diff line
@@ -29,9 +29,6 @@ 
#define __PAGE_OFFSET __PAGE_OFFSET_BASE

#include "../../mm/ident_map.c"



/* Used by pgtable.h asm code to force instruction serialization. */

unsigned long __force_order;



/* Used to track our page table allocation area. */

struct alloc_pgt_data {

	unsigned char *pgt_buf;

arch/x86/include/asm/msr-index.h

+2 −0
Original line number Diff line number Diff line
@@ -512,6 +512,8 @@ 
#define MSR_K7_HWCR			0xc0010015

#define MSR_K7_HWCR_SMMLOCK_BIT		0

#define MSR_K7_HWCR_SMMLOCK		BIT_ULL(MSR_K7_HWCR_SMMLOCK_BIT)

#define MSR_K7_HWCR_IRPERF_EN_BIT	30

#define MSR_K7_HWCR_IRPERF_EN		BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT)

#define MSR_K7_FID_VID_CTL		0xc0010041

#define MSR_K7_FID_VID_STATUS		0xc0010042

arch/x86/kernel/cpu/amd.c

+14 −0
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ 


static const int amd_erratum_383[];

static const int amd_erratum_400[];

static const int amd_erratum_1054[];

static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum);



/*
@@ -972,6 +973,15 @@ static void init_amd(struct cpuinfo_x86 *c) 
	/* AMD CPUs don't reset SS attributes on SYSRET, Xen does. */

	if (!cpu_has(c, X86_FEATURE_XENPV))

		set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS);



	/*

	 * Turn on the Instructions Retired free counter on machines not

	 * susceptible to erratum #1054 "Instructions Retired Performance

	 * Counter May Be Inaccurate".

	 */

	if (cpu_has(c, X86_FEATURE_IRPERF) &&

	    !cpu_has_amd_erratum(c, amd_erratum_1054))

		msr_set_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT);

}



#ifdef CONFIG_X86_32
@@ -1099,6 +1109,10 @@ static const int amd_erratum_400[] = 
static const int amd_erratum_383[] =

	AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));



/* #1054: Instructions Retired Performance Counter May Be Inaccurate */

static const int amd_erratum_1054[] =

	AMD_OSVW_ERRATUM(0, AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf));





static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)

{

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