Commit fc6b4204 authored by Thierry Reding's avatar Thierry Reding
Browse files

drm/dp: Do not busy-loop during link training 



Use microsecond sleeps for the clock recovery and channel equalization
delays during link training. The duration of these delays can be from
100 us up to 16 ms. It is rude to busy-loop for that amount of time.

While at it, also convert to standard coding style by putting the
opening braces in a function definition on a new line. Also switch to
using an unsigned int for the AUX read interval to match the data type
of the parameters to usleep_range().

v2: use correct multiplier for training delays (Philipp Zabel)
v3: clarify data type change in commit message

Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
Reviewed-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
Link: https://patchwork.freedesktop.org/patch/msgid/20191021143437.1477719-7-thierry.reding@gmail.com
parent 7624629d

drivers/gpu/drm/drm_dp_helper.c

+18 −12
Original line number Diff line number Diff line
@@ -120,33 +120,39 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SI 
}

EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);



void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {

	int rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &

void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])

{

	unsigned long rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &

					 DP_TRAINING_AUX_RD_MASK;



	if (rd_interval > 4)

		DRM_DEBUG_KMS("AUX interval %d, out of range (max 4)\n",

		DRM_DEBUG_KMS("AUX interval %lu, out of range (max 4)\n",

			      rd_interval);



	if (rd_interval == 0 || dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)

		udelay(100);

		rd_interval = 100;

	else

		mdelay(rd_interval * 4);

		rd_interval *= 4 * USEC_PER_MSEC;



	usleep_range(rd_interval, rd_interval * 2);

}

EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);



void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {

	int rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &

void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])

{

	unsigned long rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &

					 DP_TRAINING_AUX_RD_MASK;



	if (rd_interval > 4)

		DRM_DEBUG_KMS("AUX interval %d, out of range (max 4)\n",

		DRM_DEBUG_KMS("AUX interval %lu, out of range (max 4)\n",

			      rd_interval);



	if (rd_interval == 0)

		udelay(400);

		rd_interval = 400;

	else

		mdelay(rd_interval * 4);

		rd_interval *= 4 * USEC_PER_MSEC;



	usleep_range(rd_interval, rd_interval * 2);

}

EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);

CRA Git | Maintained and supported by SUSTech CRA and CCSE