Commit fc4a8c16 authored by Anshuman Gupta's avatar Anshuman Gupta Committed by Uma Shankar
Browse files

drm/i915: Power well id for ICL PG3 



Gen11 onwards PG3 is contains functions for pipe B,
external displays, and VGA. It make sense to add
a power well id with name ICL_DISP_PW_3 rather then
TGL_DISP_PW_3, Also PG3 power well id requires to
know if lpsp is enabled.

Reviewed-by: default avatarAnimesh Manna <animesh.manna@intel.com>
Signed-off-by: default avatarAnshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: default avatarUma Shankar <uma.shankar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200415170555.15531-2-anshuman.gupta@intel.com
parent b06ef327

drivers/gpu/drm/i915/display/intel_display_power.c

+3 −3
Original line number Diff line number Diff line
@@ -943,7 +943,7 @@ static void assert_can_enable_dc5(struct drm_i915_private *dev_priv) 


	/* Power wells at this level and above must be disabled for DC5 entry */

	if (INTEL_GEN(dev_priv) >= 12)

		high_pg = TGL_DISP_PW_3;

		high_pg = ICL_DISP_PW_3;

	else

		high_pg = SKL_DISP_PW_2;
@@ -3571,7 +3571,7 @@ static const struct i915_power_well_desc icl_power_wells[] = { 
		.name = "power well 3",

		.domains = ICL_PW_3_POWER_DOMAINS,

		.ops = &hsw_power_well_ops,

		.id = DISP_PW_ID_NONE,

		.id = ICL_DISP_PW_3,

		{

			.hsw.regs = &hsw_power_well_regs,

			.hsw.idx = ICL_PW_CTL_IDX_PW_3,
@@ -3949,7 +3949,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = { 
		.name = "power well 3",

		.domains = TGL_PW_3_POWER_DOMAINS,

		.ops = &hsw_power_well_ops,

		.id = TGL_DISP_PW_3,

		.id = ICL_DISP_PW_3,

		{

			.hsw.regs = &hsw_power_well_regs,

			.hsw.idx = ICL_PW_CTL_IDX_PW_3,

drivers/gpu/drm/i915/display/intel_display_power.h

+1 −1
Original line number Diff line number Diff line
@@ -100,7 +100,7 @@ enum i915_power_well_id { 
	SKL_DISP_PW_MISC_IO,

	SKL_DISP_PW_1,

	SKL_DISP_PW_2,

	TGL_DISP_PW_3,

	ICL_DISP_PW_3,

	SKL_DISP_DC_OFF,

};

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