Commit fc30e840 authored by Jack Zhang's avatar Jack Zhang Committed by Alex Deucher
Browse files

drm/amdgpu: optimize rlcg write for gfx_v10 



For gfx10 boards, except for nv12, other boards take mmio write
rather than rlcg write

Signed-off-by: default avatarJack Zhang <Jack.Zhang1@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c45fbe1b

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+19 −7
Original line number Diff line number Diff line
@@ -4710,12 +4710,19 @@ static int gfx_v10_0_init_csb(struct amdgpu_device *adev) 
	adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);



	/* csib */

	if (adev->asic_type == CHIP_NAVI12) {

		WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,

				adev->gfx.rlc.clear_state_gpu_addr >> 32);

		WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,

				adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);

		WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);



	} else {

		WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,

				adev->gfx.rlc.clear_state_gpu_addr >> 32);

		WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,

				adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);

		WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);

	}

	return 0;

}
@@ -5323,7 +5330,12 @@ static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 
	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);

	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);

	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);



	if (adev->asic_type == CHIP_NAVI12) {

		WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);

	} else {

		WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);

	}



	for (i = 0; i < adev->usec_timeout; i++) {

		if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)

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