Commit fbf0f5d1 authored by Ido Schimmel's avatar Ido Schimmel Committed by Jakub Kicinski
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mlxsw: reg: Add policer bandwidth limits 



Add policer bandwidth limits for both rate and burst size so that they
could be enforced by a later patch.

Signed-off-by: default avatarIdo Schimmel <idosch@mellanox.com>
Reviewed-by: default avatarJiri Pirko <jiri@mellanox.com>
Reviewed-by: default avatarPetr Machata <petrm@mellanox.com>
Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 5e126e7c

drivers/net/ethernet/mellanox/mlxsw/reg.h

+9 −0
Original line number Diff line number Diff line
@@ -3405,11 +3405,20 @@ MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4); 
 */

MLXSW_ITEM64(reg, qpcr, violate_count, 0x20, 0, 64);



/* Packets */

#define MLXSW_REG_QPCR_LOWEST_CIR	1

#define MLXSW_REG_QPCR_HIGHEST_CIR	(2 * 1000 * 1000 * 1000) /* 2Gpps */

#define MLXSW_REG_QPCR_LOWEST_CBS	4

#define MLXSW_REG_QPCR_HIGHEST_CBS	24



/* Bandwidth */

#define MLXSW_REG_QPCR_LOWEST_CIR_BITS		1024 /* bps */

#define MLXSW_REG_QPCR_HIGHEST_CIR_BITS		2000000000000ULL /* 2Tbps */

#define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP1	4

#define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP2	4

#define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP1	25

#define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP2	31



static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid,

				       enum mlxsw_reg_qpcr_ir_units ir_units,

				       bool bytes, u32 cir, u16 cbs)

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