Commit fbc44a0b authored Dec 05, 2019 by Animesh Manna Committed by Joonas Lahtinen Dec 16, 2019

drm/i915/dsb: Fix in mmio offset calculation of DSB instance



As the current usage is restricted to first DSB instance per pipe, so
existing code could not catch the issue to calculate the mmio offset
of different DSB instance per pipe. Corrected the offset calculation.

Fixes: a6e58d9a ("drm/i915/dsb: Check DSB engine status.")
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191205123513.22603-1-animesh.manna@intel.com


(cherry picked from commit d04a661a)
Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>

parent d1eef1c6

drivers/gpu/drm/i915/i915_reg.h

+1 −1

Original line number	Diff line number	Diff line
		@@ -11994,7 +11994,7 @@ enum skl_power_gate {
		/* This register controls the Display State Buffer (DSB) engines. */
		#define _DSBSL_INSTANCE_BASE 0x70B00
		#define DSBSL_INSTANCE(pipe, id) (_DSBSL_INSTANCE_BASE + \
		(pipe) * 0x1000 + (id) * 100)
		(pipe) * 0x1000 + (id) * 0x100)
		#define DSB_HEAD(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x0)
		#define DSB_TAIL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x4)
		#define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)

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