Commit fbacb15e authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/dsc: add basic hardware state readout support 



Add basic hardware state readout for DSC, and check the most relevant
details in the state checker.

v2:
- check for DSC power before reading its state
- check if source supports DSC at all

As a side effect, this should also get the power domains for the enabled
DSC on takeover, and subsequently disable DSC if it's not needed.

Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Reviewed-by: default avatarManasi Navare <manasi.d.navare@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/3fb018cf9bd9a4c275aab389b6ec0f2a4e938bb9.1575974743.git.jani.nikula@intel.com
parent deaaff49

drivers/gpu/drm/i915/display/intel_ddi.c

+2 −0
Original line number Diff line number Diff line
@@ -4294,6 +4294,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder, 
	if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))

		return;



	intel_dsc_get_config(encoder, pipe_config);



	temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));

	if (temp & TRANS_DDI_PHSYNC)

		flags |= DRM_MODE_FLAG_PHSYNC;

drivers/gpu/drm/i915/display/intel_display.c

+4 −0
Original line number Diff line number Diff line
@@ -13301,6 +13301,10 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, 
	PIPE_CONF_CHECK_I(sync_mode_slaves_mask);

	PIPE_CONF_CHECK_I(master_transcoder);



	PIPE_CONF_CHECK_I(dsc.compression_enable);

	PIPE_CONF_CHECK_I(dsc.dsc_split);

	PIPE_CONF_CHECK_I(dsc.compressed_bpp);



#undef PIPE_CONF_CHECK_X

#undef PIPE_CONF_CHECK_I

#undef PIPE_CONF_CHECK_BOOL

drivers/gpu/drm/i915/display/intel_vdsc.c

+49 −0
Original line number Diff line number Diff line
@@ -864,6 +864,55 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, 
	}

}



void intel_dsc_get_config(struct intel_encoder *encoder,

			  struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

	enum pipe pipe = crtc->pipe;

	enum intel_display_power_domain power_domain;

	intel_wakeref_t wakeref;

	u32 dss_ctl1, dss_ctl2, val;



	if (!intel_dsc_source_support(encoder, crtc_state))

		return;



	power_domain = intel_dsc_power_domain(crtc_state);



	wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);

	if (!wakeref)

		return;



	if (crtc_state->cpu_transcoder == TRANSCODER_EDP) {

		dss_ctl1 = I915_READ(DSS_CTL1);

		dss_ctl2 = I915_READ(DSS_CTL2);

	} else {

		dss_ctl1 = I915_READ(ICL_PIPE_DSS_CTL1(pipe));

		dss_ctl2 = I915_READ(ICL_PIPE_DSS_CTL2(pipe));

	}



	crtc_state->dsc.compression_enable = dss_ctl2 & LEFT_BRANCH_VDSC_ENABLE;

	if (!crtc_state->dsc.compression_enable)

		goto out;



	crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) &&

		(dss_ctl1 & JOINER_ENABLE);



	/* FIXME: add more state readout as needed */



	/* PPS1 */

	if (cpu_transcoder == TRANSCODER_EDP)

		val = I915_READ(DSCA_PICTURE_PARAMETER_SET_1);

	else

		val = I915_READ(ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));

	vdsc_cfg->bits_per_pixel = val;

	crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;

out:

	intel_display_power_put(dev_priv, power_domain, wakeref);

}



static void intel_dsc_dsi_pps_write(struct intel_encoder *encoder,

				    const struct intel_crtc_state *crtc_state)

{

drivers/gpu/drm/i915/display/intel_vdsc.h

+2 −0
Original line number Diff line number Diff line
@@ -18,6 +18,8 @@ void intel_dsc_enable(struct intel_encoder *encoder, 
void intel_dsc_disable(const struct intel_crtc_state *crtc_state);

int intel_dsc_compute_params(struct intel_encoder *encoder,

			     struct intel_crtc_state *pipe_config);

void intel_dsc_get_config(struct intel_encoder *encoder,

			  struct intel_crtc_state *crtc_state);

enum intel_display_power_domain

intel_dsc_power_domain(const struct intel_crtc_state *crtc_state);

CRA Git | Maintained and supported by SUSTech CRA and CCSE