Commit fba961ab authored by David S. Miller's avatar David S. Miller
Browse files

Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net 



Lots of overlapping changes.  Also on the net-next side
the XDP state management is handled more in the generic
layers so undo the 'net' nfp fix which isn't applicable
in net-next.

Include a necessary change by Jakub Kicinski, with log message:

====================
cls_bpf no longer takes care of offload tracking.  Make sure
netdevsim performs necessary checks.  This fixes a warning
caused by TC trying to remove a filter it has not added.

Signed-off-by: default avatarJakub Kicinski <jakub.kicinski@netronome.com>
Reviewed-by: default avatarQuentin Monnet <quentin.monnet@netronome.com>
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 0a80f0c2 ead68f21

Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt

+0 −2
Original line number Diff line number Diff line
@@ -13,7 +13,6 @@ Required properties: 
                 at25df321a

                 at25df641

                 at26df081a

                 en25s64

                 mr25h128

                 mr25h256

                 mr25h10
@@ -33,7 +32,6 @@ Required properties: 
                 s25fl008k

                 s25fl064k

                 sst25vf040b

                 sst25wf040b

                 m25p40

                 m25p80

                 m25p16

Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt

+12 −6
Original line number Diff line number Diff line
@@ -12,24 +12,30 @@ Required properties: 
  - "fsl,imx53-ecspi" for SPI compatible with the one integrated on i.MX53 and later Soc

- reg : Offset and length of the register set for the device

- interrupts : Should contain CSPI/eCSPI interrupt

- cs-gpios : Specifies the gpio pins to be used for chipselects.

- clocks : Clock specifiers for both ipg and per clocks.

- clock-names : Clock names should include both "ipg" and "per"

See the clock consumer binding,

	Documentation/devicetree/bindings/clock/clock-bindings.txt

- dmas: DMA specifiers for tx and rx dma. See the DMA client binding,

		Documentation/devicetree/bindings/dma/dma.txt

- dma-names: DMA request names should include "tx" and "rx" if present.



Obsolete properties:

- fsl,spi-num-chipselects : Contains the number of the chipselect

Recommended properties:

- cs-gpios : GPIOs to use as chip selects, see spi-bus.txt.  While the native chip

select lines can be used, they appear to always generate a pulse between each

word of a transfer.  Most use cases will require GPIO based chip selects to

generate a valid transaction.



Optional properties:

- num-cs :  Number of total chip selects, see spi-bus.txt.

- dmas: DMA specifiers for tx and rx dma. See the DMA client binding,

Documentation/devicetree/bindings/dma/dma.txt.

- dma-names: DMA request names, if present, should include "tx" and "rx".

- fsl,spi-rdy-drctl: Integer, representing the value of DRCTL, the register

controlling the SPI_READY handling. Note that to enable the DRCTL consideration,

the SPI_READY mode-flag needs to be set too.

Valid values are: 0 (disabled), 1 (edge-triggered burst) and 2 (level-triggered burst).



Obsolete properties:

- fsl,spi-num-chipselects : Contains the number of the chipselect



Example:



ecspi@70010000 {

Makefile

+1 −1
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ 
VERSION = 4

PATCHLEVEL = 15

SUBLEVEL = 0

EXTRAVERSION = -rc3

EXTRAVERSION = -rc4

NAME = Fearless Coyote



# *DOCUMENTATION*

arch/arm/lib/csumpartialcopyuser.S

+4 −0
Original line number Diff line number Diff line
@@ -85,7 +85,11 @@ 
		.pushsection .text.fixup,"ax"

		.align	4

9001:		mov	r4, #-EFAULT

#ifdef CONFIG_CPU_SW_DOMAIN_PAN

		ldr	r5, [sp, #9*4]		@ *err_ptr

#else

		ldr	r5, [sp, #8*4]		@ *err_ptr

#endif

		str	r4, [r5]

		ldmia	sp, {r1, r2}		@ retrieve dst, len

		add	r2, r2, r1

arch/arm64/kvm/hyp/debug-sr.c

+3 −0
Original line number Diff line number Diff line
@@ -74,6 +74,9 @@ static void __hyp_text __debug_save_spe_nvhe(u64 *pmscr_el1) 
{

	u64 reg;



	/* Clear pmscr in case of early return */

	*pmscr_el1 = 0;



	/* SPE present on this CPU? */

	if (!cpuid_feature_extract_unsigned_field(read_sysreg(id_aa64dfr0_el1),

						  ID_AA64DFR0_PMSVER_SHIFT))

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