clk: renesas: r8a774b1: Add RPC clocks (fb9805c5) · Commits · 戴 / test

Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it, as well as the RPC-IF module clock, in the RZ/G2N (R8A774B1) CPG/MSSR driver. Inspired by commit ("clk: renesas: r8a77980: Add RPC clocks"). Signed-off-by:

Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by:

Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20201016121709.8447-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by:

Geert Uytterhoeven <geert+renesas@glider.be>

drivers/clk/renesas/r8a774b1-cpg-mssr.c

+8 −0

Original line number	Diff line number	Diff line
		@@ -40,6 +40,7 @@ enum clk_ids {
		CLK_S2,
		CLK_S3,
		CLK_SDSRC,
		CLK_RPCSRC,
		CLK_RINT,

		/* Module Clocks */
		@@ -65,6 +66,12 @@ static const struct cpg_core_clk r8a774b1_core_clks[] __initconst = {
		DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
		DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
		DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
		DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),

		DEF_BASE("rpc", R8A774B1_CLK_RPC, CLK_TYPE_GEN3_RPC,
		CLK_RPCSRC),
		DEF_BASE("rpcd2", R8A774B1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
		R8A774B1_CLK_RPC),

		DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),

		@@ -196,6 +203,7 @@ static const struct mssr_mod_clk r8a774b1_mod_clks[] __initconst = {
		DEF_MOD("can-fd", 914, R8A774B1_CLK_S3D2),
		DEF_MOD("can-if1", 915, R8A774B1_CLK_S3D4),
		DEF_MOD("can-if0", 916, R8A774B1_CLK_S3D4),
		DEF_MOD("rpc-if", 917, R8A774B1_CLK_RPCD2),
		DEF_MOD("i2c6", 918, R8A774B1_CLK_S0D6),
		DEF_MOD("i2c5", 919, R8A774B1_CLK_S0D6),
		DEF_MOD("i2c-dvfs", 926, R8A774B1_CLK_CP),

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