Commit fb87a298 authored by Paolo Ciarrocchi's avatar Paolo Ciarrocchi Committed by Ingo Molnar
Browse files

x86: coding style fixes to arch/x86/kernel/cpu/amd.c 



Before:
   total: 42 errors, 26 warnings, 350 lines checked
After:
   total: 0 errors, 26 warnings, 352 lines checked

No code changed:

arch/x86/kernel/cpu/amd.o:

   text	   data	    bss	    dec	    hex	filename
   1936	    328	      0	   2264	    8d8	amd.o.before
   1936	    328	      0	   2264	    8d8	amd.o.after

md5:
   873430a88faaf31bb4bbfe3a2a691e45  amd.o.before.asm
   873430a88faaf31bb4bbfe3a2a691e45  amd.o.after.asm

Signed-off-by: default avatarPaolo Ciarrocchi <paolo.ciarrocchi@gmail.com>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent f9751827

arch/x86/kernel/cpu/amd.c

+48 −46
Original line number Diff line number Diff line
@@ -81,7 +81,8 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c) 
#ifdef CONFIG_SMP

	unsigned long long value;



	/* Disable TLB flush filter by setting HWCR.FFDIS on K8

	/*

	 * Disable TLB flush filter by setting HWCR.FFDIS on K8

	 * bit 6 of msr C001_0015

	 *

	 * Errata 63 for SH-B3 steppings
@@ -102,14 +103,15 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c) 
	 *	no bus pipeline)

	 */



	/* Bit 31 in normal CPUID used for nonstandard 3DNow ID;

	   3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */

	/*

	 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;

	 * DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway

	 */

	clear_bit(0*32+31, c->x86_capability);



	r = get_model_name(c);



	switch(c->x86)

	{

	switch (c->x86) {

	case 4:

		/*

		 * General Systems BIOSen alias the cpu frequency registers
@@ -126,8 +128,7 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c) 
			}

			break;

	case 5:

			if( c->x86_model < 6 )

			{

			if (c->x86_model < 6) {

				/* Based on AMD doc 20734R - June 2000 */

				if (c->x86_model == 0) {

					clear_bit(X86_FEATURE_APIC, c->x86_capability);
@@ -219,7 +220,8 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c) 
			break;

	case 6: /* An Athlon/Duron */



			/* Bit 15 of Athlon specific MSR 15, needs to be 0

			/*

			 * Bit 15 of Athlon specific MSR 15, needs to be 0

			 * to enable SSE on Palomino/Morgan/Barton CPU's.

			 * If the BIOS didn't enable it already, enable it here.

			 */
@@ -233,7 +235,8 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c) 
				}

			}



			/* It's been determined by AMD that Athlons since model 8 stepping 1

			/*

			 * It's been determined by AMD that Athlons since model 8 stepping 1

			 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx

			 * As per AMD technical note 27212 0.2

			 */
@@ -264,9 +267,8 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c) 


	display_cacheinfo(c);



	if (cpuid_eax(0x80000000) >= 0x80000008) {

	if (cpuid_eax(0x80000000) >= 0x80000008)

		c->x86_max_cores = (cpuid_ecx(0x80000008) & 0xff) + 1;

	}



#ifdef CONFIG_X86_HT

	/*

CRA Git | Maintained and supported by SUSTech CRA and CCSE