Commit fb71a336 authored by Guchun Chen's avatar Guchun Chen Committed by Alex Deucher
Browse files

drm/amdgpu: move umc offset to one new header file for Arcturus 



Code refactor and no functional change.

Fixes: 4cf781c2 ("drm/amdgpu: Added RAS UMC error query support for Arcturus")
Signed-off-by: default avatarGuchun Chen <guchun.chen@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent e3250f2d

drivers/gpu/drm/amd/amdgpu/umc_v6_1.c

+1 −16
Original line number Diff line number Diff line
@@ -28,17 +28,10 @@ 
#include "rsmu/rsmu_0_0_2_sh_mask.h"

#include "umc/umc_6_1_1_offset.h"

#include "umc/umc_6_1_1_sh_mask.h"

#include "umc/umc_6_1_2_offset.h"



#define smnMCA_UMC0_MCUMC_ADDRT0	0x50f10



/* UMC 6_1_2 register offsets */

#define mmUMCCH0_0_EccErrCntSel_ARCT                 0x0360

#define mmUMCCH0_0_EccErrCntSel_ARCT_BASE_IDX        1

#define mmUMCCH0_0_EccErrCnt_ARCT                    0x0361

#define mmUMCCH0_0_EccErrCnt_ARCT_BASE_IDX           1

#define mmMCA_UMC_UMC0_MCUMC_STATUST0_ARCT           0x03c2

#define mmMCA_UMC_UMC0_MCUMC_STATUST0_ARCT_BASE_IDX  1



/*

 * (addr / 256) * 8192, the higher 26 bits in ErrorAddr

 * is the index of 8KB block
@@ -105,7 +98,6 @@ static void umc_v6_1_query_correctable_error_count(struct amdgpu_device *adev, 


	if (adev->asic_type == CHIP_ARCTURUS) {

		/* UMC 6_1_2 registers */



		ecc_err_cnt_sel_addr =

			SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel_ARCT);

		ecc_err_cnt_addr =
@@ -114,7 +106,6 @@ static void umc_v6_1_query_correctable_error_count(struct amdgpu_device *adev, 
			SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0_ARCT);

	} else {

		/* UMC 6_1_1 registers */



		ecc_err_cnt_sel_addr =

			SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel);

		ecc_err_cnt_addr =
@@ -164,12 +155,10 @@ static void umc_v6_1_querry_uncorrectable_error_count(struct amdgpu_device *adev 


	if (adev->asic_type == CHIP_ARCTURUS) {

		/* UMC 6_1_2 registers */



		mc_umc_status_addr =

			SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0_ARCT);

	} else {

		/* UMC 6_1_1 registers */



		mc_umc_status_addr =

			SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);

	}
@@ -211,12 +200,10 @@ static void umc_v6_1_query_error_address(struct amdgpu_device *adev, 


	if (adev->asic_type == CHIP_ARCTURUS) {

		/* UMC 6_1_2 registers */



		mc_umc_status_addr =

			SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0_ARCT);

	} else {

		/* UMC 6_1_1 registers */



		mc_umc_status_addr =

			SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);

	}
@@ -282,14 +269,12 @@ static void umc_v6_1_err_cnt_init_per_channel(struct amdgpu_device *adev, 


	if (adev->asic_type == CHIP_ARCTURUS) {

		/* UMC 6_1_2 registers */



		ecc_err_cnt_sel_addr =

			SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel_ARCT);

		ecc_err_cnt_addr =

			SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCnt_ARCT);

	} else {

		/* UMC 6_1_1 registers */



		ecc_err_cnt_sel_addr =

			SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel);

		ecc_err_cnt_addr =

drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_2_offset.h

0 → 100644
+31 −0
Original line number Diff line number Diff line 
/*

 * Copyright (C) 2019  Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included

 * in all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS

 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN

 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN

 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

 */

#ifndef _umc_6_1_2_OFFSET_HEADER

#define _umc_6_1_2_OFFSET_HEADER



#define mmUMCCH0_0_EccErrCntSel_ARCT                                     0x0360

#define mmUMCCH0_0_EccErrCntSel_ARCT_BASE_IDX                            1

#define mmUMCCH0_0_EccErrCnt_ARCT                                        0x0361

#define mmUMCCH0_0_EccErrCnt_ARCT_BASE_IDX                               1

#define mmMCA_UMC_UMC0_MCUMC_STATUST0_ARCT                               0x03c2

#define mmMCA_UMC_UMC0_MCUMC_STATUST0_ARCT_BASE_IDX                      1



#endif

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