dt: bindings: Document ZynqMP DDRC in Synopsys documentation

Binding for Synopsys IntelliDDR Multi Protocol Memory Controller

This controller has an optional ECC support in half-bus width (16-bit)

configuration. The ECC controller corrects one bit error and detects

two bit errors.

The ZynqMP DDR ECC controller has an optional ECC support in 64-bit and 32-bit

bus width configurations.

The Zynq DDR ECC controller has an optional ECC support in half-bus width

(16-bit) configuration.

These both ECC controllers correct single bit ECC errors and detect double bit

ECC errors.

Required properties:

 - compatible: Should be 'xlnx,zynq-ddrc-a05'

 - reg: Base address and size of the controllers memory area

 - compatible: One of:

	- 'xlnx,zynq-ddrc-a05' : Zynq DDR ECC controller

	- 'xlnx,zynqmp-ddrc-2.40a' : ZynqMP DDR ECC controller

 - reg: Should contain DDR controller registers location and length.

Required properties for "xlnx,zynqmp-ddrc-2.40a":

 - interrupts: Property with a value describing the interrupt number.

Example:

	memory-controller@f8006000 {

		compatible = "xlnx,zynq-ddrc-a05";

		reg = <0xf8006000 0x1000>;

	};

	mc: memory-controller@fd070000 {

		compatible = "xlnx,zynqmp-ddrc-2.40a";

		reg = <0x0 0xfd070000 0x0 0x30000>;

		interrupt-parent = <&gic>;

		interrupts = <0 112 4>;

	};