Commit fb2b1ea3 authored by Su Sung Chung's avatar Su Sung Chung Committed by Alex Deucher
Browse files

drm/amd/display: program v_update and v_ready with proper field 



[WHY]
There are two different variables used to calculate v_update and v_ready,
one for validation and the other for performance parameter calculation.
Before the variable for validation was used which caused underflow on
1080edp with vsr enabled

[HOW]
program v_update and v_ready with the variables for performance parameter
calculation

Signed-off-by: default avatarSu Sung Chung <su.chung@amd.com>
Reviewed-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: default avatarBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c2791297

drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c

+4 −4
Original line number Diff line number Diff line
@@ -1625,11 +1625,11 @@ void dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performan 
				else {

					v->dsty_after_scaler = 0.0;

				}

				v->v_update_offset_pix =dcn_bw_ceil2(v->htotal[k] / 4.0, 1.0);

				v->v_update_offset_pix[k] = dcn_bw_ceil2(v->htotal[k] / 4.0, 1.0);

				v->total_repeater_delay_time = v->max_inter_dcn_tile_repeaters * (2.0 / v->dppclk + 3.0 / v->dispclk);

				v->v_update_width_pix = (14.0 / v->dcf_clk_deep_sleep + 12.0 / v->dppclk + v->total_repeater_delay_time) * v->pixel_clock[k];

				v->v_ready_offset_pix =dcn_bw_max2(150.0 / v->dppclk, v->total_repeater_delay_time + 20.0 / v->dcf_clk_deep_sleep + 10.0 / v->dppclk) * v->pixel_clock[k];

				v->t_setup = (v->v_update_offset_pix + v->v_update_width_pix + v->v_ready_offset_pix) / v->pixel_clock[k];

				v->v_update_width_pix[k] = (14.0 / v->dcf_clk_deep_sleep + 12.0 / v->dppclk + v->total_repeater_delay_time) * v->pixel_clock[k];

				v->v_ready_offset_pix[k] = dcn_bw_max2(150.0 / v->dppclk, v->total_repeater_delay_time + 20.0 / v->dcf_clk_deep_sleep + 10.0 / v->dppclk) * v->pixel_clock[k];

				v->t_setup = (v->v_update_offset_pix[k] + v->v_update_width_pix[k] + v->v_ready_offset_pix[k]) / v->pixel_clock[k];

				v->v_startup[k] =dcn_bw_min2(v->v_startup_lines, v->max_vstartup_lines[k]);

				if (v->prefetch_mode == 0.0) {

					v->t_wait =dcn_bw_max3(v->dram_clock_change_latency + v->urgent_latency, v->sr_enter_plus_exit_time, v->urgent_latency);

drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c

+6 −6
Original line number Diff line number Diff line
@@ -1096,9 +1096,9 @@ bool dcn_validate_bandwidth( 
			if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)

				continue;



			pipe->pipe_dlg_param.vupdate_width = v->v_update_width[input_idx][v->dpp_per_plane[input_idx] == 2 ? 1 : 0];

			pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset[input_idx][v->dpp_per_plane[input_idx] == 2 ? 1 : 0];

			pipe->pipe_dlg_param.vready_offset = v->v_ready_offset[input_idx][v->dpp_per_plane[input_idx] == 2 ? 1 : 0];

			pipe->pipe_dlg_param.vupdate_width = v->v_update_width_pix[input_idx];

			pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset_pix[input_idx];

			pipe->pipe_dlg_param.vready_offset = v->v_ready_offset_pix[input_idx];

			pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx];



			pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total;
@@ -1137,9 +1137,9 @@ bool dcn_validate_bandwidth( 
					 TIMING_3D_FORMAT_SIDE_BY_SIDE))) {

					if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {

						/* update previously split pipe */

						hsplit_pipe->pipe_dlg_param.vupdate_width = v->v_update_width[input_idx][v->dpp_per_plane[input_idx] == 2 ? 1 : 0];

						hsplit_pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset[input_idx][v->dpp_per_plane[input_idx] == 2 ? 1 : 0];

						hsplit_pipe->pipe_dlg_param.vready_offset = v->v_ready_offset[input_idx][v->dpp_per_plane[input_idx] == 2 ? 1 : 0];

						hsplit_pipe->pipe_dlg_param.vupdate_width = v->v_update_width_pix[input_idx];

						hsplit_pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset_pix[input_idx];

						hsplit_pipe->pipe_dlg_param.vready_offset = v->v_ready_offset_pix[input_idx];

						hsplit_pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx];



						hsplit_pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total;

drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h

+3 −3
Original line number Diff line number Diff line
@@ -504,10 +504,10 @@ struct dcn_bw_internal_vars { 
	float prefetch_mode;

	float dstx_after_scaler;

	float dsty_after_scaler;

	float v_update_offset_pix;

	float v_update_offset_pix[number_of_planes_minus_one + 1];

	float total_repeater_delay_time;

	float v_update_width_pix;

	float v_ready_offset_pix;

	float v_update_width_pix[number_of_planes_minus_one + 1];

	float v_ready_offset_pix[number_of_planes_minus_one + 1];

	float t_setup;

	float t_wait;

	float bandwidth_available_for_immediate_flip;

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