Commit fb24ea52 authored by Will Deacon's avatar Will Deacon
Browse files

drivers: Remove explicit invocations of mmiowb() 



mmiowb() is now implied by spin_unlock() on architectures that require
it, so there is no reason to call it from driver code. This patch was
generated using coccinelle:

	@mmiowb@
	@@
	- mmiowb();

and invoked as:

$ for d in drivers include/linux/qed sound; do \
spatch --include-headers --sp-file mmiowb.cocci --dir $d --in-place; done

NOTE: mmiowb() has only ever guaranteed ordering in conjunction with
spin_unlock(). However, pairing each mmiowb() removal in this patch with
the corresponding call to spin_unlock() is not at all trivial, so there
is a small chance that this change may regress any drivers incorrectly
relying on mmiowb() to order MMIO writes between CPUs using lock-free
synchronisation. If you've ended up bisecting to this commit, you can
reintroduce the mmiowb() calls using wmb() instead, which should restore
the old behaviour on all architectures other than some esoteric ia64
systems.

Acked-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent 949b8c72

drivers/crypto/cavium/nitrox/nitrox_reqmgr.c

+0 −4
Original line number Diff line number Diff line
@@ -303,8 +303,6 @@ static void post_se_instr(struct nitrox_softreq *sr, 


	/* Ring doorbell with count 1 */

	writeq(1, cmdq->dbell_csr_addr);

	/* orders the doorbell rings */

	mmiowb();



	cmdq->write_idx = incr_index(idx, 1, ndev->qlen);
@@ -599,8 +597,6 @@ void pkt_slc_resp_tasklet(unsigned long data) 
	 * MSI-X interrupt generates if Completion count > Threshold

	 */

	writeq(slc_cnts.value, cmdq->compl_cnt_csr_addr);

	/* order the writes */

	mmiowb();



	if (atomic_read(&cmdq->backlog_count))

		schedule_work(&cmdq->backlog_qflush);

drivers/dma/txx9dmac.c

+0 −3
Original line number Diff line number Diff line
@@ -327,7 +327,6 @@ static void txx9dmac_reset_chan(struct txx9dmac_chan *dc) 
	channel_writel(dc, SAIR, 0);

	channel_writel(dc, DAIR, 0);

	channel_writel(dc, CCR, 0);

	mmiowb();

}



/* Called with dc->lock held and bh disabled */
@@ -954,7 +953,6 @@ static void txx9dmac_chain_dynamic(struct txx9dmac_chan *dc, 
	dma_sync_single_for_device(chan2parent(&dc->chan),

				   prev->txd.phys, ddev->descsize,

				   DMA_TO_DEVICE);

	mmiowb();

	if (!(channel_readl(dc, CSR) & TXX9_DMA_CSR_CHNEN) &&

	    channel_read_CHAR(dc) == prev->txd.phys)

		/* Restart chain DMA */
@@ -1080,7 +1078,6 @@ static void txx9dmac_free_chan_resources(struct dma_chan *chan) 
static void txx9dmac_off(struct txx9dmac_dev *ddev)

{

	dma_writel(ddev, MCR, 0);

	mmiowb();

}



static int __init txx9dmac_chan_probe(struct platform_device *pdev)

drivers/firewire/ohci.c

+0 −1
Original line number Diff line number Diff line
@@ -2939,7 +2939,6 @@ static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels) 
	reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);

	reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);

	reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);

	mmiowb();

	ohci->mc_channels = channels;

}

drivers/gpu/drm/i915/intel_hdmi.c

+0 −10
Original line number Diff line number Diff line
@@ -182,7 +182,6 @@ static void g4x_write_infoframe(struct intel_encoder *encoder, 


	I915_WRITE(VIDEO_DIP_CTL, val);



	mmiowb();

	for (i = 0; i < len; i += 4) {

		I915_WRITE(VIDEO_DIP_DATA, *data);

		data++;
@@ -190,7 +189,6 @@ static void g4x_write_infoframe(struct intel_encoder *encoder, 
	/* Write every possible data byte to force correct ECC calculation. */

	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)

		I915_WRITE(VIDEO_DIP_DATA, 0);

	mmiowb();



	val |= g4x_infoframe_enable(type);

	val &= ~VIDEO_DIP_FREQ_MASK;
@@ -237,7 +235,6 @@ static void ibx_write_infoframe(struct intel_encoder *encoder, 


	I915_WRITE(reg, val);



	mmiowb();

	for (i = 0; i < len; i += 4) {

		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);

		data++;
@@ -245,7 +242,6 @@ static void ibx_write_infoframe(struct intel_encoder *encoder, 
	/* Write every possible data byte to force correct ECC calculation. */

	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)

		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);

	mmiowb();



	val |= g4x_infoframe_enable(type);

	val &= ~VIDEO_DIP_FREQ_MASK;
@@ -298,7 +294,6 @@ static void cpt_write_infoframe(struct intel_encoder *encoder, 


	I915_WRITE(reg, val);



	mmiowb();

	for (i = 0; i < len; i += 4) {

		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);

		data++;
@@ -306,7 +301,6 @@ static void cpt_write_infoframe(struct intel_encoder *encoder, 
	/* Write every possible data byte to force correct ECC calculation. */

	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)

		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);

	mmiowb();



	val |= g4x_infoframe_enable(type);

	val &= ~VIDEO_DIP_FREQ_MASK;
@@ -352,7 +346,6 @@ static void vlv_write_infoframe(struct intel_encoder *encoder, 


	I915_WRITE(reg, val);



	mmiowb();

	for (i = 0; i < len; i += 4) {

		I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);

		data++;
@@ -360,7 +353,6 @@ static void vlv_write_infoframe(struct intel_encoder *encoder, 
	/* Write every possible data byte to force correct ECC calculation. */

	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)

		I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);

	mmiowb();



	val |= g4x_infoframe_enable(type);

	val &= ~VIDEO_DIP_FREQ_MASK;
@@ -406,7 +398,6 @@ static void hsw_write_infoframe(struct intel_encoder *encoder, 
	val &= ~hsw_infoframe_enable(type);

	I915_WRITE(ctl_reg, val);



	mmiowb();

	for (i = 0; i < len; i += 4) {

		I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,

					    type, i >> 2), *data);
@@ -416,7 +407,6 @@ static void hsw_write_infoframe(struct intel_encoder *encoder, 
	for (; i < data_size; i += 4)

		I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,

					    type, i >> 2), 0);

	mmiowb();



	val |= hsw_infoframe_enable(type);

	I915_WRITE(ctl_reg, val);

drivers/ide/tx4939ide.c

+0 −2
Original line number Diff line number Diff line
@@ -156,7 +156,6 @@ static u16 tx4939ide_check_error_ints(ide_hwif_t *hwif) 
		u16 sysctl = tx4939ide_readw(base, TX4939IDE_Sys_Ctl);



		tx4939ide_writew(sysctl | 0x4000, base, TX4939IDE_Sys_Ctl);

		mmiowb();

		/* wait 12GBUSCLK (typ. 60ns @ GBUS200MHz, max 270ns) */

		ndelay(270);

		tx4939ide_writew(sysctl, base, TX4939IDE_Sys_Ctl);
@@ -396,7 +395,6 @@ static void tx4939ide_init_hwif(ide_hwif_t *hwif) 


	/* Soft Reset */

	tx4939ide_writew(0x8000, base, TX4939IDE_Sys_Ctl);

	mmiowb();

	/* at least 20 GBUSCLK (typ. 100ns @ GBUS200MHz, max 450ns) */

	ndelay(450);

	tx4939ide_writew(0x0000, base, TX4939IDE_Sys_Ctl);

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