Commit fb1cecd4 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven Committed by Simon Horman
Browse files

ARM: dts: r8a7790: Add L2 cache-controller nodes 



Add device nodes for the L2 caches, and link the CPU nodes to them.

The L2 cache for the Cortex-A15 CPU cores is 2 MiB large (organized as
128 KiB x 16 ways).

The L2 cache for the Cortex-A7 CPU cores is 512 KiB large (organized as
64 KiB x 8 ways).

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent c86a4b62

arch/arm/boot/dts/r8a7790.dtsi

+20 −0
Original line number Diff line number Diff line
@@ -52,6 +52,7 @@ 
			voltage-tolerance = <1>; /* 1% */

			clocks = <&cpg_clocks R8A7790_CLK_Z>;

			clock-latency = <300000>; /* 300 us */

			next-level-cache = <&L2_CA15>;



			/* kHz - uV - OPPs unknown yet */

			operating-points = <1400000 1000000>,
@@ -67,6 +68,7 @@ 
			compatible = "arm,cortex-a15";

			reg = <1>;

			clock-frequency = <1300000000>;

			next-level-cache = <&L2_CA15>;

		};



		cpu2: cpu@2 {
@@ -74,6 +76,7 @@ 
			compatible = "arm,cortex-a15";

			reg = <2>;

			clock-frequency = <1300000000>;

			next-level-cache = <&L2_CA15>;

		};



		cpu3: cpu@3 {
@@ -81,6 +84,7 @@ 
			compatible = "arm,cortex-a15";

			reg = <3>;

			clock-frequency = <1300000000>;

			next-level-cache = <&L2_CA15>;

		};



		cpu4: cpu@4 {
@@ -88,6 +92,7 @@ 
			compatible = "arm,cortex-a7";

			reg = <0x100>;

			clock-frequency = <780000000>;

			next-level-cache = <&L2_CA7>;

		};



		cpu5: cpu@5 {
@@ -95,6 +100,7 @@ 
			compatible = "arm,cortex-a7";

			reg = <0x101>;

			clock-frequency = <780000000>;

			next-level-cache = <&L2_CA7>;

		};



		cpu6: cpu@6 {
@@ -102,6 +108,7 @@ 
			compatible = "arm,cortex-a7";

			reg = <0x102>;

			clock-frequency = <780000000>;

			next-level-cache = <&L2_CA7>;

		};



		cpu7: cpu@7 {
@@ -109,6 +116,7 @@ 
			compatible = "arm,cortex-a7";

			reg = <0x103>;

			clock-frequency = <780000000>;

			next-level-cache = <&L2_CA7>;

		};

	};
@@ -131,6 +139,18 @@ 
		};

	};



	L2_CA15: cache-controller@0 {

		compatible = "cache";

		cache-unified;

		cache-level = <2>;

	};



	L2_CA7: cache-controller@1 {

		compatible = "cache";

		cache-unified;

		cache-level = <2>;

	};



	gic: interrupt-controller@f1001000 {

		compatible = "arm,gic-400";

		#interrupt-cells = <3>;

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