Commit fb0f33fd authored by Krish Sadhukhan's avatar Krish Sadhukhan Committed by Paolo Bonzini
Browse files

KVM: nSVM: CR3 MBZ bits are only 63:52 



Commit 761e4169 created a wrong mask for the
CR3 MBZ bits. According to APM vol 2, only the upper 12 bits are MBZ.

Fixes: 761e4169 ("KVM: nSVM: Check that MBZ bits in CR3 and CR4 are not set on vmrun of nested guests", 2020-07-08)
Signed-off-by: default avatarKrish Sadhukhan <krish.sadhukhan@oracle.com>
Message-Id: <20200829004824.4577-2-krish.sadhukhan@oracle.com>
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent a9e2e0ae

arch/x86/kvm/svm/nested.c

+1 −1
Original line number Diff line number Diff line
@@ -237,7 +237,7 @@ static bool nested_vmcb_checks(struct vcpu_svm *svm, struct vmcb *vmcb12) 
	} else {

		if (!(vmcb12->save.cr4 & X86_CR4_PAE) ||

		    !(vmcb12->save.cr0 & X86_CR0_PE) ||

		    (vmcb12->save.cr3 & MSR_CR3_LONG_RESERVED_MASK))

		    (vmcb12->save.cr3 & MSR_CR3_LONG_MBZ_MASK))

			return false;

	}

	if (kvm_valid_cr4(&svm->vcpu, vmcb12->save.cr4))

arch/x86/kvm/svm/svm.h

+1 −1
Original line number Diff line number Diff line
@@ -339,7 +339,7 @@ static inline bool gif_set(struct vcpu_svm *svm) 
/* svm.c */

#define MSR_CR3_LEGACY_RESERVED_MASK		0xfe7U

#define MSR_CR3_LEGACY_PAE_RESERVED_MASK	0x7U

#define MSR_CR3_LONG_RESERVED_MASK		0xfff0000000000fe7U

#define MSR_CR3_LONG_MBZ_MASK			0xfff0000000000000U

#define MSR_INVALID				0xffffffffU



u32 svm_msrpm_offset(u32 msr);

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