Commit faff3d8e authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branch 'clk-renesas' into clk-next 

* clk-renesas: (36 commits)
  clk: renesas: r7s9210: Add SPI clocks
  clk: renesas: r7s9210: Move table update to separate function
  clk: renesas: r7s9210: Convert some clocks to early
  clk: renesas: cpg-mssr: Add early clock support
  clk: renesas: r8a77970: Add TPU clock
  clk: renesas: r8a77990: Fix incorrect PLL0 divider in comment
  dt-bindings: clock: renesas: cpg-mssr: Document r8a774c0
  clk: renesas: cpg-mssr: Add r8a774c0 support
  clk: renesas: Add r8a774c0 CPG Core Clock Definitions
  clk: renesas: r8a7743: Add r8a7744 support
  clk: renesas: Add r8a7744 CPG Core Clock Definitions
  dt-bindings: clock: renesas: cpg-mssr: Document r8a7744 binding
  dt-bindings: clock: renesas: Convert to SPDX identifiers
  clk: renesas: cpg-mssr: Add R7S9210 support
  clk: renesas: r8a77970: Add TMU clocks
  clk: renesas: r8a77970: Add CMT clocks
  clk: renesas: r9a06g032: Fix UART34567 clock rate
  clk: renesas: r8a77970: Add SD0H/SD0 clocks for SDHI
  clk: renesas: r8a77980: Add CMT clocks
  clk: renesas: r8a77990: Add missing I2C7 clock
  ...
parents 9710ee14 be783cc8

Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt

+11 −6
Original line number Diff line number Diff line
@@ -13,9 +13,13 @@ They provide the following functionalities: 


Required Properties:

  - compatible: Must be one of:

      - "renesas,r7s9210-cpg-mssr" for the r7s9210 SoC (RZ/A2)

      - "renesas,r8a7743-cpg-mssr" for the r8a7743 SoC (RZ/G1M)

      - "renesas,r8a7744-cpg-mssr" for the r8a7744 SoC (RZ/G1N)

      - "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E)

      - "renesas,r8a77470-cpg-mssr" for the r8a77470 SoC (RZ/G1C)

      - "renesas,r8a774a1-cpg-mssr" for the r8a774a1 SoC (RZ/G2M)

      - "renesas,r8a774c0-cpg-mssr" for the r8a774c0 SoC (RZ/G2E)

      - "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2)

      - "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W)

      - "renesas,r8a7792-cpg-mssr" for the r8a7792 SoC (R-Car V2H)
@@ -35,12 +39,13 @@ Required Properties: 
  - clocks: References to external parent clocks, one entry for each entry in

    clock-names

  - clock-names: List of external parent clock names. Valid names are:

      - "extal" (r8a7743, r8a7745, r8a77470, r8a7790, r8a7791, r8a7792,

		 r8a7793, r8a7794, r8a7795, r8a7796, r8a77965, r8a77970,

		 r8a77980, r8a77990, r8a77995)

      - "extalr" (r8a7795, r8a7796, r8a77965, r8a77970, r8a77980)

      - "usb_extal" (r8a7743, r8a7745, r8a77470, r8a7790, r8a7791, r8a7793,

		     r8a7794)

      - "extal" (r7s9210, r8a7743, r8a7744, r8a7745, r8a77470, r8a774a1,

		 r8a774c0, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,

		 r8a7795, r8a7796, r8a77965, r8a77970, r8a77980, r8a77990,

		 r8a77995)

      - "extalr" (r8a774a1, r8a7795, r8a7796, r8a77965, r8a77970, r8a77980)

      - "usb_extal" (r8a7743, r8a7744, r8a7745, r8a77470, r8a7790, r8a7791,

		     r8a7793, r8a7794)



  - #clock-cells: Must be 2

      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"

drivers/clk/renesas/Kconfig

+16 −1
Original line number Diff line number Diff line
@@ -5,11 +5,14 @@ config CLK_RENESAS 
	default y if ARCH_RENESAS

	select CLK_EMEV2 if ARCH_EMEV2

	select CLK_RZA1 if ARCH_R7S72100

	select CLK_R7S9210 if ARCH_R7S9210

	select CLK_R8A73A4 if ARCH_R8A73A4

	select CLK_R8A7740 if ARCH_R8A7740

	select CLK_R8A7743 if ARCH_R8A7743

	select CLK_R8A7743 if ARCH_R8A7743 || ARCH_R8A7744

	select CLK_R8A7745 if ARCH_R8A7745

	select CLK_R8A77470 if ARCH_R8A77470

	select CLK_R8A774A1 if ARCH_R8A774A1

	select CLK_R8A774C0 if ARCH_R8A774C0

	select CLK_R8A7778 if ARCH_R8A7778

	select CLK_R8A7779 if ARCH_R8A7779

	select CLK_R8A7790 if ARCH_R8A7790
@@ -47,6 +50,10 @@ config CLK_RZA1 
	bool "RZ/A1H clock support" if COMPILE_TEST

	select CLK_RENESAS_CPG_MSTP



config CLK_R7S9210

	bool "RZ/A2 clock support" if COMPILE_TEST

	select CLK_RENESAS_CPG_MSSR



config CLK_R8A73A4

	bool "R-Mobile APE6 clock support" if COMPILE_TEST

	select CLK_RENESAS_CPG_MSTP
@@ -69,6 +76,14 @@ config CLK_R8A77470 
	bool "RZ/G1C clock support" if COMPILE_TEST

	select CLK_RCAR_GEN2_CPG



config CLK_R8A774A1

	bool "RZ/G2M clock support" if COMPILE_TEST

	select CLK_RCAR_GEN3_CPG



config CLK_R8A774C0

	bool "RZ/G2E clock support" if COMPILE_TEST

	select CLK_RCAR_GEN3_CPG



config CLK_R8A7778

	bool "R-Car M1A clock support" if COMPILE_TEST

	select CLK_RENESAS_CPG_MSTP

drivers/clk/renesas/Makefile

+3 −0
Original line number Diff line number Diff line
@@ -2,11 +2,14 @@ 
# SoC

obj-$(CONFIG_CLK_EMEV2)			+= clk-emev2.o

obj-$(CONFIG_CLK_RZA1)			+= clk-rz.o

obj-$(CONFIG_CLK_R7S9210)		+= r7s9210-cpg-mssr.o

obj-$(CONFIG_CLK_R8A73A4)		+= clk-r8a73a4.o

obj-$(CONFIG_CLK_R8A7740)		+= clk-r8a7740.o

obj-$(CONFIG_CLK_R8A7743)		+= r8a7743-cpg-mssr.o

obj-$(CONFIG_CLK_R8A7745)		+= r8a7745-cpg-mssr.o

obj-$(CONFIG_CLK_R8A77470)		+= r8a77470-cpg-mssr.o

obj-$(CONFIG_CLK_R8A774A1)		+= r8a774a1-cpg-mssr.o

obj-$(CONFIG_CLK_R8A774C0)		+= r8a774c0-cpg-mssr.o

obj-$(CONFIG_CLK_R8A7778)		+= clk-r8a7778.o

obj-$(CONFIG_CLK_R8A7779)		+= clk-r8a7779.o

obj-$(CONFIG_CLK_R8A7790)		+= r8a7790-cpg-mssr.o

drivers/clk/renesas/r7s9210-cpg-mssr.c

0 → 100644
+217 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * R7S9210 Clock Pulse Generator / Module Standby

 *

 * Based on r8a7795-cpg-mssr.c

 *

 * Copyright (C) 2018 Chris Brandt

 * Copyright (C) 2018 Renesas Electronics Corp.

 *

 */



#include <linux/clk.h>

#include <linux/clk-provider.h>

#include <dt-bindings/clock/r7s9210-cpg-mssr.h>

#include "renesas-cpg-mssr.h"



#define CPG_FRQCR	0x00



static u8 cpg_mode;



/* Internal Clock ratio table */

static const struct {

	unsigned int i;

	unsigned int g;

	unsigned int b;

	unsigned int p1;

	/* p0 is always 32 */;

} ratio_tab[5] = {	/* I,  G,  B, P1 */

			{  2,  4,  8, 16},	/* FRQCR = 0x012 */

			{  4,  4,  8, 16},	/* FRQCR = 0x112 */

			{  8,  4,  8, 16},	/* FRQCR = 0x212 */

			{ 16,  8, 16, 16},	/* FRQCR = 0x322 */

			{ 16, 16, 32, 32},	/* FRQCR = 0x333 */

			};



enum rz_clk_types {

	CLK_TYPE_RZA_MAIN = CLK_TYPE_CUSTOM,

	CLK_TYPE_RZA_PLL,

};



enum clk_ids {

	/* Core Clock Outputs exported to DT */

	LAST_DT_CORE_CLK = R7S9210_CLK_P0,



	/* External Input Clocks */

	CLK_EXTAL,



	/* Internal Core Clocks */

	CLK_MAIN,

	CLK_PLL,



	/* Module Clocks */

	MOD_CLK_BASE

};



static struct cpg_core_clk r7s9210_early_core_clks[] = {

	/* External Clock Inputs */

	DEF_INPUT("extal",     CLK_EXTAL),



	/* Internal Core Clocks */

	DEF_BASE(".main",       CLK_MAIN, CLK_TYPE_RZA_MAIN, CLK_EXTAL),

	DEF_BASE(".pll",       CLK_PLL, CLK_TYPE_RZA_PLL, CLK_MAIN),



	/* Core Clock Outputs */

	DEF_FIXED("p1c",    R7S9210_CLK_P1C,   CLK_PLL,         16, 1),

};



static const struct mssr_mod_clk r7s9210_early_mod_clks[] __initconst = {

	DEF_MOD_STB("ostm2",	 34,	R7S9210_CLK_P1C),

	DEF_MOD_STB("ostm1",	 35,	R7S9210_CLK_P1C),

	DEF_MOD_STB("ostm0",	 36,	R7S9210_CLK_P1C),

};



static struct cpg_core_clk r7s9210_core_clks[] = {

	/* Core Clock Outputs */

	DEF_FIXED("i",      R7S9210_CLK_I,     CLK_PLL,          2, 1),

	DEF_FIXED("g",      R7S9210_CLK_G,     CLK_PLL,          4, 1),

	DEF_FIXED("b",      R7S9210_CLK_B,     CLK_PLL,          8, 1),

	DEF_FIXED("p1",     R7S9210_CLK_P1,    CLK_PLL,         16, 1),

	DEF_FIXED("p0",     R7S9210_CLK_P0,    CLK_PLL,         32, 1),

};



static const struct mssr_mod_clk r7s9210_mod_clks[] __initconst = {

	DEF_MOD_STB("scif4",	 43,	R7S9210_CLK_P1C),

	DEF_MOD_STB("scif3",	 44,	R7S9210_CLK_P1C),

	DEF_MOD_STB("scif2",	 45,	R7S9210_CLK_P1C),

	DEF_MOD_STB("scif1",	 46,	R7S9210_CLK_P1C),

	DEF_MOD_STB("scif0",	 47,	R7S9210_CLK_P1C),



	DEF_MOD_STB("ether1",	 64,	R7S9210_CLK_B),

	DEF_MOD_STB("ether0",	 65,	R7S9210_CLK_B),



	DEF_MOD_STB("i2c3",	 84,	R7S9210_CLK_P1),

	DEF_MOD_STB("i2c2",	 85,	R7S9210_CLK_P1),

	DEF_MOD_STB("i2c1",	 86,	R7S9210_CLK_P1),

	DEF_MOD_STB("i2c0",	 87,	R7S9210_CLK_P1),



	DEF_MOD_STB("spi2",	 95,	R7S9210_CLK_P1),

	DEF_MOD_STB("spi1",	 96,	R7S9210_CLK_P1),

	DEF_MOD_STB("spi0",	 97,	R7S9210_CLK_P1),

};



/* The clock dividers in the table vary based on DT and register settings */

static void __init r7s9210_update_clk_table(struct clk *extal_clk,

					    void __iomem *base)

{

	int i;

	u16 frqcr;

	u8 index;



	/* If EXTAL is above 12MHz, then we know it is Mode 1 */

	if (clk_get_rate(extal_clk) > 12000000)

		cpg_mode = 1;



	frqcr = clk_readl(base + CPG_FRQCR) & 0xFFF;

	if (frqcr == 0x012)

		index = 0;

	else if (frqcr == 0x112)

		index = 1;

	else if (frqcr == 0x212)

		index = 2;

	else if (frqcr == 0x322)

		index = 3;

	else if (frqcr == 0x333)

		index = 4;

	else

		BUG_ON(1);	/* Illegal FRQCR value */



	for (i = 0; i < ARRAY_SIZE(r7s9210_core_clks); i++) {

		switch (r7s9210_core_clks[i].id) {

		case R7S9210_CLK_I:

			r7s9210_core_clks[i].div = ratio_tab[index].i;

			break;

		case R7S9210_CLK_G:

			r7s9210_core_clks[i].div = ratio_tab[index].g;

			break;

		case R7S9210_CLK_B:

			r7s9210_core_clks[i].div = ratio_tab[index].b;

			break;

		case R7S9210_CLK_P1:

		case R7S9210_CLK_P1C:

			r7s9210_core_clks[i].div = ratio_tab[index].p1;

			break;

		case R7S9210_CLK_P0:

			r7s9210_core_clks[i].div = 32;

			break;

		}

	}

}



struct clk * __init rza2_cpg_clk_register(struct device *dev,

	const struct cpg_core_clk *core, const struct cpg_mssr_info *info,

	struct clk **clks, void __iomem *base,

	struct raw_notifier_head *notifiers)

{

	struct clk *parent;

	unsigned int mult = 1;

	unsigned int div = 1;



	parent = clks[core->parent];

	if (IS_ERR(parent))

		return ERR_CAST(parent);



	switch (core->id) {

	case CLK_MAIN:

		break;



	case CLK_PLL:

		if (cpg_mode)

			mult = 44;	/* Divider 1 is 1/2 */

		else

			mult = 88;	/* Divider 1 is 1 */

		break;



	default:

		return ERR_PTR(-EINVAL);

	}



	if (core->id == CLK_MAIN)

		r7s9210_update_clk_table(parent, base);



	return clk_register_fixed_factor(NULL, core->name,

					 __clk_get_name(parent), 0, mult, div);

}



const struct cpg_mssr_info r7s9210_cpg_mssr_info __initconst = {

	/* Early Clocks */

	.early_core_clks = r7s9210_early_core_clks,

	.num_early_core_clks = ARRAY_SIZE(r7s9210_early_core_clks),

	.early_mod_clks = r7s9210_early_mod_clks,

	.num_early_mod_clks = ARRAY_SIZE(r7s9210_early_mod_clks),



	/* Core Clocks */

	.core_clks = r7s9210_core_clks,

	.num_core_clks = ARRAY_SIZE(r7s9210_core_clks),

	.last_dt_core_clk = LAST_DT_CORE_CLK,

	.num_total_core_clks = MOD_CLK_BASE,



	/* Module Clocks */

	.mod_clks = r7s9210_mod_clks,

	.num_mod_clks = ARRAY_SIZE(r7s9210_mod_clks),

	.num_hw_mod_clks = 11 * 32, /* includes STBCR0 which doesn't exist */



	/* Callbacks */

	.cpg_clk_register = rza2_cpg_clk_register,



	/* RZ/A2 has Standby Control Registers */

	.stbyctrl = true,

};



static void __init r7s9210_cpg_mssr_early_init(struct device_node *np)

{

	cpg_mssr_early_init(np, &r7s9210_cpg_mssr_info);

}



CLK_OF_DECLARE_DRIVER(cpg_mstp_clks, "renesas,r7s9210-cpg-mssr",

		      r7s9210_cpg_mssr_early_init);

drivers/clk/renesas/r8a7743-cpg-mssr.c

+12 −1
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ 
#include <linux/device.h>

#include <linux/init.h>

#include <linux/kernel.h>

#include <linux/of.h>

#include <linux/soc/renesas/rcar-rst.h>



#include <dt-bindings/clock/r8a7743-cpg-mssr.h>
@@ -34,7 +35,7 @@ enum clk_ids { 
	MOD_CLK_BASE

};



static const struct cpg_core_clk r8a7743_core_clks[] __initconst = {

static struct cpg_core_clk r8a7743_core_clks[] __initdata = {

	/* External Clock Inputs */

	DEF_INPUT("extal",	CLK_EXTAL),

	DEF_INPUT("usb_extal",	CLK_USB_EXTAL),
@@ -235,6 +236,8 @@ static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = { 
static int __init r8a7743_cpg_mssr_init(struct device *dev)

{

	const struct rcar_gen2_cpg_pll_config *cpg_pll_config;

	struct device_node *np = dev->of_node;

	unsigned int i;

	u32 cpg_mode;

	int error;
@@ -244,6 +247,14 @@ static int __init r8a7743_cpg_mssr_init(struct device *dev) 


	cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];



	if (of_device_is_compatible(np, "renesas,r8a7744-cpg-mssr")) {

		/* RZ/G1N uses a 1/5 divider for ZG */

		for (i = 0; i < ARRAY_SIZE(r8a7743_core_clks); i++)

			if (r8a7743_core_clks[i].id == R8A7743_CLK_ZG) {

				r8a7743_core_clks[i].div = 5;

				break;

			}

	}

	return rcar_gen2_cpg_init(cpg_pll_config, 2, cpg_mode);

}

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