Commit fafda335 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'imx7ulp-dt-4.21' of... 

Merge tag 'imx7ulp-dt-4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt

i.MX7ULP device tree for 4.21:
 - It includes the initial device tree for i.MX7ULP SoC and EVK board
   support.

* tag 'imx7ulp-dt-4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux

:
  ARM: dts: imx: add imx7ulp evk support
  ARM: dts: imx: add common imx7ulp dtsi support
  dt-bindings: fsl: add imx7ulp pm related components bindings
  dt-bindings: fsl: add compatible for imx7ulp evk
  clk: imx: add imx7ulp clk driver
  clk: imx: implement new clk_hw based APIs
  clk: imx: make mux parent strings const
  dt-bindings: clock: add imx7ulp clock binding doc
  clk: imx: add imx7ulp composite clk support
  clk: imx: add pfdv2 support
  clk: imx: add pllv4 support
  clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support
  clk: imx: add gatable clock divider support

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 2b646456 a73900b8

Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.txt

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Freescale i.MX7ULP Power Management Components

----------------------------------------------



The Multi-System Mode Controller (MSMC) is responsible for sequencing

the MCU into and out of all stop and run power modes. Specifically, it

monitors events to trigger transitions between power modes while

controlling the power, clocks, and memories of the MCU to achieve the

power consumption and functionality of that mode.



The WFI or WFE instruction is used to invoke a Sleep, Deep Sleep or

Standby modes for either Cortex family. Run, Wait, and Stop are the

common terms used for the primary operating modes of Kinetis

microcontrollers.



Required properties:

- compatible:	Should be "fsl,imx7ulp-smc1".

- reg:		Specifies base physical address and size of the register sets.



Example:

smc1: smc1@40410000 {

	compatible = "fsl,imx7ulp-smc1";

	reg = <0x40410000 0x1000>;

};

Documentation/devicetree/bindings/arm/fsl.txt

+8 −0
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@@ -101,6 +101,10 @@ i.MX7 SabreSD Board 
Required root node properties:

    - compatible = "fsl,imx7d-sdb", "fsl,imx7d";



i.MX7ULP Evaluation Kit

Required root node properties:

    - compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp";



Generic i.MX boards

-------------------
@@ -123,6 +127,10 @@ i.MX6q generic board 
Required root node properties:

    - compatible = "fsl,imx6q";



i.MX7ULP generic board

Required root node properties:

    - compatible = "fsl,imx7ulp";



Freescale Vybrid Platform Device Tree Bindings

----------------------------------------------

Documentation/devicetree/bindings/clock/imx7ulp-clock.txt

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* Clock bindings for Freescale i.MX7ULP



i.MX7ULP Clock functions are under joint control of the System

Clock Generation (SCG) modules, Peripheral Clock Control (PCC)

modules, and Core Mode Controller (CMC)1 blocks



The clocking scheme provides clear separation between M4 domain

and A7 domain. Except for a few clock sources shared between two

domains, such as the System Oscillator clock, the Slow IRC (SIRC),

and and the Fast IRC clock (FIRCLK), clock sources and clock

management are separated and contained within each domain.



M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.

A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.



Note: this binding doc is only for A7 clock domain.



System Clock Generation (SCG) modules:

---------------------------------------------------------------------

The System Clock Generation (SCG) is responsible for clock generation

and distribution across this device. Functions performed by the SCG

include: clock reference selection, generation of clock used to derive

processor, system, peripheral bus and external memory interface clocks,

source selection for peripheral clocks and control of power saving

clock gating mode.



Required properties:



- compatible:	Should be "fsl,imx7ulp-scg1".

- reg : 	Should contain registers location and length.

- #clock-cells:	Should be <1>.

- clocks:	Should contain the fixed input clocks.

- clock-names:  Should contain the following clock names:

		"rosc", "sosc", "sirc", "firc", "upll", "mpll".



Peripheral Clock Control (PCC) modules:

---------------------------------------------------------------------

The Peripheral Clock Control (PCC) is responsible for clock selection,

optional division and clock gating mode for peripherals in their

respected power domain



Required properties:

- compatible:	Should be one of:

		  "fsl,imx7ulp-pcc2",

		  "fsl,imx7ulp-pcc3".

- reg : 	Should contain registers location and length.

- #clock-cells:	Should be <1>.

- clocks:	Should contain the fixed input clocks.

- clock-names:  Should contain the following clock names:

		"nic1_bus_clk", "nic1_clk", "ddr_clk", "apll_pfd2",

		"apll_pfd1", "apll_pfd0", "upll", "sosc_bus_clk",

		"mpll", "firc_bus_clk", "rosc", "spll_bus_clk";



The clock consumer should specify the desired clock by having the clock

ID in its "clocks" phandle cell.

See include/dt-bindings/clock/imx7ulp-clock.h

for the full list of i.MX7ULP clock IDs of each module.



Examples:



#include <dt-bindings/clock/imx7ulp-clock.h>



scg1: scg1@403e0000 {

	compatible = "fsl,imx7ulp-scg1;

	reg = <0x403e0000 0x10000>;

	clocks = <&rosc>, <&sosc>, <&sirc>,

		 <&firc>, <&upll>, <&mpll>;

	clock-names = "rosc", "sosc", "sirc",

		      "firc", "upll", "mpll";

	#clock-cells = <1>;

};



pcc2: pcc2@403f0000 {

	compatible = "fsl,imx7ulp-pcc2";

	reg = <0x403f0000 0x10000>;

	#clock-cells = <1>;

	clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,

		 <&scg1 IMX7ULP_CLK_NIC1_DIV>,

		 <&scg1 IMX7ULP_CLK_DDR_DIV>,

		 <&scg1 IMX7ULP_CLK_APLL_PFD2>,

		 <&scg1 IMX7ULP_CLK_APLL_PFD1>,

		 <&scg1 IMX7ULP_CLK_APLL_PFD0>,

		 <&scg1 IMX7ULP_CLK_UPLL>,

		 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,

		 <&scg1 IMX7ULP_CLK_MIPI_PLL>,

		 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,

		 <&scg1 IMX7ULP_CLK_ROSC>,

		 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;

	clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",

		      "apll_pfd2", "apll_pfd1", "apll_pfd0",

		      "upll", "sosc_bus_clk", "mpll",

		      "firc_bus_clk", "rosc", "spll_bus_clk";

};



usdhc1: usdhc@40380000 {

	compatible = "fsl,imx7ulp-usdhc";

	reg = <0x40380000 0x10000>;

	interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,

		 <&scg1 IMX7ULP_CLK_NIC1_DIV>,

		 <&pcc2 IMX7ULP_CLK_USDHC1>;

	clock-names ="ipg", "ahb", "per";

	bus-width = <4>;

};

arch/arm/boot/dts/Makefile

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@@ -581,6 +581,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \ 
	imx7d-sdb-sht11.dtb \

	imx7s-colibri-eval-v3.dtb \

	imx7s-warp.dtb

dtb-$(CONFIG_SOC_IMX7ULP) += \

	imx7ulp-evk.dtb

dtb-$(CONFIG_SOC_LS1021A) += \

	ls1021a-moxa-uc-8410a.dtb \

	ls1021a-qds.dtb \

arch/arm/boot/dts/imx7ulp-evk.dts

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// SPDX-License-Identifier: GPL-2.0+

/*

 * Copyright 2016 Freescale Semiconductor, Inc.

 * Copyright 2017-2018 NXP

 *   Dong Aisheng <aisheng.dong@nxp.com>

 */



/dts-v1/;



#include "imx7ulp.dtsi"



/ {

	model = "NXP i.MX7ULP EVK";

	compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp";



	chosen {

		stdout-path = &lpuart4;

	};



	memory@60000000 {

		device_type = "memory";

		reg = <0x60000000 0x40000000>;

	};



	reg_vsd_3v3: regulator-vsd-3v3 {

		compatible = "regulator-fixed";

		regulator-name = "VSD_3V3";

		regulator-min-microvolt = <3300000>;

		regulator-max-microvolt = <3300000>;

		pinctrl-names = "default";

		pinctrl-0 = <&pinctrl_usdhc0_rst>;

		gpio = <&gpio_ptd 0 GPIO_ACTIVE_HIGH>;

		enable-active-high;

	};

};



&lpuart4 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_lpuart4>;

	status = "okay";

};



&usdhc0 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_usdhc0>;

	cd-gpios = <&gpio_ptc 10 GPIO_ACTIVE_LOW>;

	vmmc-supply = <&reg_vsd_3v3>;

	status = "okay";

};



&iomuxc1 {

	pinctrl_lpuart4: lpuart4grp {

		fsl,pins = <

			IMX7ULP_PAD_PTC3__LPUART4_RX	0x3

			IMX7ULP_PAD_PTC2__LPUART4_TX	0x3

		>;

		bias-pull-up;

	};



	pinctrl_usdhc0: usdhc0grp {

		fsl,pins = <

			IMX7ULP_PAD_PTD1__SDHC0_CMD	0x43

			IMX7ULP_PAD_PTD2__SDHC0_CLK	0x40

			IMX7ULP_PAD_PTD7__SDHC0_D3	0x43

			IMX7ULP_PAD_PTD8__SDHC0_D2	0x43

			IMX7ULP_PAD_PTD9__SDHC0_D1	0x43

			IMX7ULP_PAD_PTD10__SDHC0_D0	0x43

			IMX7ULP_PAD_PTC10__PTC10	0x3	/* CD */

		>;

	};



	pinctrl_usdhc0_rst: usdhc0-gpio-rst-grp {

		fsl,pins = <

			IMX7ULP_PAD_PTD0__PTD0		0x3

		>;

	};

};

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