Commit fa9ae305 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'sunxi-clk-for-5.6' of... 

Merge tag 'sunxi-clk-for-5.6' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner

Pull Allwinner clk driver updates from Maxime Ripard:

Our usual set of patches for sunxi, with a bunch of them required to
enable the MBUS controller, and two patches to enable cpufreq on the
A64.

* tag 'sunxi-clk-for-5.6' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi: a23/a33: Export the MIPI PLL
  clk: sunxi: a31: Export the MIPI PLL
  clk: sunxi-ng: a64: export CLK_CPUX clock for DVFS
  clk: sunxi-ng: add mux and pll notifiers for A64 CPU clock
  clk: sunxi-ng: r40: Export MBUS clock
  clk: sunxi: use of_device_get_match_data
parents e42617b8 9c232d32

drivers/clk/sunxi-ng/ccu-sun50i-a64.c

+27 −1
Original line number Diff line number Diff line
@@ -921,11 +921,26 @@ static const struct sunxi_ccu_desc sun50i_a64_ccu_desc = { 
	.num_resets	= ARRAY_SIZE(sun50i_a64_ccu_resets),

};



static struct ccu_pll_nb sun50i_a64_pll_cpu_nb = {

	.common	= &pll_cpux_clk.common,

	/* copy from pll_cpux_clk */

	.enable	= BIT(31),

	.lock	= BIT(28),

};



static struct ccu_mux_nb sun50i_a64_cpu_nb = {

	.common		= &cpux_clk.common,

	.cm		= &cpux_clk.mux,

	.delay_us	= 1, /* > 8 clock cycles at 24 MHz */

	.bypass_index	= 1, /* index of 24 MHz oscillator */

};



static int sun50i_a64_ccu_probe(struct platform_device *pdev)

{

	struct resource *res;

	void __iomem *reg;

	u32 val;

	int ret;



	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	reg = devm_ioremap_resource(&pdev->dev, res);
@@ -939,7 +954,18 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev) 


	writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);



	return sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_a64_ccu_desc);

	ret = sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_a64_ccu_desc);

	if (ret)

		return ret;



	/* Gate then ungate PLL CPU after any rate changes */

	ccu_pll_notifier_register(&sun50i_a64_pll_cpu_nb);



	/* Reparent CPU during PLL CPU rate changes */

	ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,

				  &sun50i_a64_cpu_nb);



	return 0;

}



static const struct of_device_id sun50i_a64_ccu_ids[] = {

drivers/clk/sunxi-ng/ccu-sun50i-a64.h

+0 −1
Original line number Diff line number Diff line
@@ -36,7 +36,6 @@ 
#define CLK_PLL_HSIC			18

#define CLK_PLL_DE			19

#define CLK_PLL_DDR1			20

#define CLK_CPUX			21

#define CLK_AXI				22

#define CLK_APB				23

#define CLK_AHB1			24

drivers/clk/sunxi-ng/ccu-sun6i-a31.h

+3 −1
Original line number Diff line number Diff line
@@ -32,7 +32,9 @@ 
/* The PLL_VIDEO1_2X clock is exported */



#define CLK_PLL_GPU		14

#define CLK_PLL_MIPI		15



/* The PLL_VIDEO1_2X clock is exported */



#define CLK_PLL9		16

#define CLK_PLL10		17

drivers/clk/sunxi-ng/ccu-sun8i-a23-a33.h

+3 −1
Original line number Diff line number Diff line
@@ -24,7 +24,9 @@ 
#define CLK_PLL_PERIPH		10

#define CLK_PLL_PERIPH_2X	11

#define CLK_PLL_GPU		12

#define CLK_PLL_MIPI		13



/* The PLL MIPI clock is exported */



#define CLK_PLL_HSIC		14

#define CLK_PLL_DE		15

#define CLK_PLL_DDR1		16

drivers/clk/sunxi-ng/ccu-sun8i-r40.h

+0 −4
Original line number Diff line number Diff line
@@ -55,10 +55,6 @@ 


/* Some more module clocks are exported */



#define CLK_MBUS		155



/* Another bunch of module clocks are exported */



#define CLK_NUMBER		(CLK_OUTB + 1)



#endif /* _CCU_SUN8I_R40_H_ */

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