Commit fa8ff601 authored Feb 03, 2016 by Paul Burton Committed by Ralf Baechle Mar 29, 2016

MIPS: Fix MSA ld unaligned failure cases



Copying the content of an MSA vector from user memory may involve TLB
faults & mapping in pages. This will fail when preemption is disabled
due to an inability to acquire mmap_sem from do_page_fault, which meant
such vector loads to unmapped pages would always fail to be emulated.
Fix this by disabling preemption later only around the updating of
vector register state.

This change does however introduce a race between performing the load
into thread context & the thread being preempted, saving its current
live context & clobbering the loaded value. This should be a rare
occureence, so optimise for the fast path by simply repeating the load if
we are preempted.

Additionally if the copy failed then the failure path was taken with
preemption left disabled, leading to the kernel typically encountering
further issues around sleeping whilst atomic. The change to where
preemption is disabled avoids this issue.

Fixes: e4aa1f15 "MIPS: MSA unaligned memory access support"
Reported-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Cc: James Cowgill <James.Cowgill@imgtec.com>
Cc: Markos Chandras <markos.chandras@imgtec.com>
Cc: stable <stable@vger.kernel.org> # v4.3
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/12345/


Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

parent 19fb5818

arch/mips/kernel/unaligned.c

+30 −21

Original line number	Diff line number	Diff line
		@@ -885,7 +885,7 @@ static void emulate_load_store_insn(struct pt_regs *regs,
		{
		union mips_instruction insn;
		unsigned long value;
		unsigned int res;
		unsigned int res, preempted;
		unsigned long origpc;
		unsigned long orig31;
		void __user *fault_addr = NULL;
		@@ -1226,12 +1226,17 @@ static void emulate_load_store_insn(struct pt_regs *regs,
		if (!access_ok(VERIFY_READ, addr, sizeof(*fpr)))
		goto sigbus;

		do {
		/*
		* Disable preemption to avoid a race between copying
		* state from userland, migrating to another CPU and
		* updating the hardware vector register below.
		* If we have live MSA context keep track of
		* whether we get preempted in order to avoid
		* the register context we load being clobbered
		* by the live context as it's saved during
		* preemption. If we don't have live context
		* then it can't be saved to clobber the value
		* we load.
		*/
		preempt_disable();
		preempted = test_thread_flag(TIF_USEDMSA);

		res = __copy_from_user_inatomic(fpr, addr,
		sizeof(*fpr));
		@@ -1239,14 +1244,18 @@ static void emulate_load_store_insn(struct pt_regs *regs,
		goto fault;

		/*
		* Update the hardware register if it is in use by the
		* task in this quantum, in order to avoid having to
		* save & restore the whole vector context.
		* Update the hardware register if it is in use
		* by the task in this quantum, in order to
		* avoid having to save & restore the whole
		* vector context.
		*/
		if (test_thread_flag(TIF_USEDMSA))
		preempt_disable();
		if (test_thread_flag(TIF_USEDMSA)) {
		write_msa_wr(wd, fpr, df);

		preempted = 0;
		}
		preempt_enable();
		} while (preempted);
		break;

		case msa_st_op:

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