Commit fa8962a8 authored by Haojian Zhuang's avatar Haojian Zhuang Committed by Kevin Hilman
Browse files

ARM: dts: enable hi4511 with device tree 



Enable Hisilicon Hi4511 development platform with device tree support.

Signed-off-by: default avatarHaojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: default avatarKevin Hilman <khilman@linaro.org>
parent 2c7268c7

arch/arm/boot/dts/Makefile

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@@ -66,6 +66,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ 
	exynos5420-smdk5420.dtb \

	exynos5440-sd5v1.dtb \

	exynos5440-ssdk5440.dtb

dtb-$(CONFIG_ARCH_HI3xxx) += hi4511.dtb

dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \

	ecx-2000.dtb

dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \

arch/arm/boot/dts/hi3620.dtsi

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/*

 * Hisilicon Ltd. Hi3620 SoC

 *

 * Copyright (C) 2012-2013 Hisilicon Ltd.

 * Copyright (C) 2012-2013 Linaro Ltd.

 *

 * Author: Haojian Zhuang <haojian.zhuang@linaro.org>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * publishhed by the Free Software Foundation.

 */



/include/ "skeleton.dtsi"



/ {

	aliases {

		serial0 = &uart0;

		serial1 = &uart1;

		serial2 = &uart2;

		serial3 = &uart3;

		serial4 = &uart4;

	};



	pclk: clk {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <26000000>;

		clock-output-names = "apb_pclk";

	};



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a9";

			reg = <0x0>;

			next-level-cache = <&L2>;

		};

	};



	amba {

		#address-cells = <1>;

		#size-cells = <1>;

		compatible = "arm,amba-bus";

		interrupt-parent = <&gic>;

		ranges = <0 0xfc000000 0x2000000>;



		L2: l2-cache {

			compatible = "arm,pl310-cache";

			reg = <0xfc10000 0x100000>;

			interrupts = <0 15 4>;

			cache-unified;

			cache-level = <2>;

		};



		gic: interrupt-controller@1000 {

			compatible = "arm,cortex-a9-gic";

			#interrupt-cells = <3>;

			#address-cells = <0>;

			interrupt-controller;

			/* gic dist base, gic cpu base */

			reg = <0x1000 0x1000>, <0x100 0x100>;

		};



		dual_timer0: dual_timer@800000 {

			compatible = "arm,sp804", "arm,primecell";

			reg = <0x800000 0x1000>;

			/* timer00 & timer01 */

			interrupts = <0 0 4>, <0 1 4>;

			clocks = <&pclk>;

			clock-names = "apb_pclk";

			status = "disabled";

		};



		dual_timer1: dual_timer@801000 {

			compatible = "arm,sp804", "arm,primecell";

			reg = <0x801000 0x1000>;

			/* timer10 & timer11 */

			interrupts = <0 2 4>, <0 3 4>;

			clocks = <&pclk>;

			clock-names = "apb_pclk";

			status = "disabled";

		};



		dual_timer2: dual_timer@a01000 {

			compatible = "arm,sp804", "arm,primecell";

			reg = <0xa01000 0x1000>;

			/* timer20 & timer21 */

			interrupts = <0 4 4>, <0 5 4>;

			clocks = <&pclk>;

			clock-names = "apb_pclk";

			status = "disabled";

		};



		dual_timer3: dual_timer@a02000 {

			compatible = "arm,sp804", "arm,primecell";

			reg = <0xa02000 0x1000>;

			/* timer30 & timer31 */

			interrupts = <0 6 4>, <0 7 4>;

			clocks = <&pclk>;

			clock-names = "apb_pclk";

			status = "disabled";

		};



		dual_timer4: dual_timer@a03000 {

			compatible = "arm,sp804", "arm,primecell";

			reg = <0xa03000 0x1000>;

			/* timer40 & timer41 */

			interrupts = <0 96 4>, <0 97 4>;

			clocks = <&pclk>;

			clock-names = "apb_pclk";

			status = "disabled";

		};



		uart0: uart@b00000 {

			compatible = "arm,pl011", "arm,primecell";

			reg = <0xb00000 0x1000>;

			interrupts = <0 20 4>;

			clocks = <&pclk>;

			clock-names = "apb_pclk";

			status = "disabled";

		};



		uart1: uart@b01000 {

			compatible = "arm,pl011", "arm,primecell";

			reg = <0xb01000 0x1000>;

			interrupts = <0 21 4>;

			clocks = <&pclk>;

			clock-names = "apb_pclk";

			status = "disabled";

		};



		uart2: uart@b02000 {

			compatible = "arm,pl011", "arm,primecell";

			reg = <0xb02000 0x1000>;

			interrupts = <0 22 4>;

			clocks = <&pclk>;

			clock-names = "apb_pclk";

			status = "disabled";

		};



		uart3: uart@b03000 {

			compatible = "arm,pl011", "arm,primecell";

			reg = <0xb03000 0x1000>;

			interrupts = <0 23 4>;

			clocks = <&pclk>;

			clock-names = "apb_pclk";

			status = "disabled";

		};



		uart4: uart@b04000 {

			compatible = "arm,pl011", "arm,primecell";

			reg = <0xb04000 0x1000>;

			interrupts = <0 24 4>;

			clocks = <&pclk>;

			clock-names = "apb_pclk";

			status = "disabled";

		};



		gpio0: gpio@806000 {

			compatible = "arm,pl061", "arm,primecell";

			reg = <0x806000 0x1000>;

			interrupts = <0 64 0x4>;

			gpio-controller;

			#gpio-cells = <2>;

			gpio-ranges = <	&pmx0 2 0 1 &pmx0 3 0 1 &pmx0 4 0 1

					&pmx0 5 0 1 &pmx0 6 1 1 &pmx0 7 2 1>;

			interrupt-controller;

			#interrupt-cells = <2>;

			clocks = <&pclk>;

			clock-names = "apb_pclk";

		};



		gpio1: gpio@807000 {

			compatible = "arm,pl061", "arm,primecell";

			reg = <0x807000 0x1000>;

			interrupts = <0 65 0x4>;

			gpio-controller;

			#gpio-cells = <2>;

			gpio-ranges = <	&pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1

					&pmx0 3 3 1 &pmx0 4 3 1 &pmx0 5 4 1

					&pmx0 6 5 1 &pmx0 7 6 1>;

			interrupt-controller;

			#interrupt-cells = <2>;

			clocks = <&pclk>;

			clock-names = "apb_pclk";

		};



		gpio2: gpio@808000 {

			compatible = "arm,pl061", "arm,primecell";

			reg = <0x808000 0x1000>;

			interrupts = <0 66 0x4>;

			gpio-controller;

			#gpio-cells = <2>;

			gpio-ranges = <	&pmx0 0 7 1 &pmx0 1 8 1 &pmx0 2 9 1

					&pmx0 3 10 1 &pmx0 4 3 1 &pmx0 5 3 1

					&pmx0 6 3 1 &pmx0 7 3 1>;

			interrupt-controller;

			#interrupt-cells = <2>;

			clocks = <&pclk>;

			clock-names = "apb_pclk";

		};



		gpio3: gpio@809000 {

			compatible = "arm,pl061", "arm,primecell";

			reg = <0x809000 0x1000>;

			interrupts = <0 67 0x4>;

			gpio-controller;

			#gpio-cells = <2>;

			gpio-ranges = <	&pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1

					&pmx0 3 3 1 &pmx0 4 11 1 &pmx0 5 11 1

					&pmx0 6 11 1 &pmx0 7 11 1>;

			interrupt-controller;

			#interrupt-cells = <2>;

			clocks = <&pclk>;

			clock-names = "apb_pclk";

		};



		gpio4: gpio@80a000 {

			compatible = "arm,pl061", "arm,primecell";

			reg = <0x80a000 0x1000>;

			interrupts = <0 68 0x4>;

			gpio-controller;

			#gpio-cells = <2>;

			gpio-ranges = <	&pmx0 0 11 1 &pmx0 1 11 1 &pmx0 2 11 1

					&pmx0 3 11 1 &pmx0 4 12 1 &pmx0 5 12 1

					&pmx0 6 13 1 &pmx0 7 13 1>;

			interrupt-controller;

			#interrupt-cells = <2>;

			clocks = <&pclk>;

			clock-names = "apb_pclk";

		};



		gpio5: gpio@80b000 {

			compatible = "arm,pl061", "arm,primecell";

			reg = <0x80b000 0x1000>;

			interrupts = <0 69 0x4>;

			gpio-controller;

			#gpio-cells = <2>;

			gpio-ranges = <	&pmx0 0 14 1 &pmx0 1 15 1 &pmx0 2 16 1

					&pmx0 3 16 1 &pmx0 4 16 1 &pmx0 5 16 1

					&pmx0 6 16 1 &pmx0 7 16 1>;

			interrupt-controller;

			#interrupt-cells = <2>;

			clocks = <&pclk>;

			clock-names = "apb_pclk";

		};



		gpio6: gpio@80c000 {

			compatible = "arm,pl061", "arm,primecell";

			reg = <0x80c000 0x1000>;

			interrupts = <0 70 0x4>;

			gpio-controller;

			#gpio-cells = <2>;

			gpio-ranges = <	&pmx0 0 16 1 &pmx0 1 16 1 &pmx0 2 17 1

					&pmx0 3 17 1 &pmx0 4 18 1 &pmx0 5 18 1

					&pmx0 6 18 1 &pmx0 7 19 1>;

			interrupt-controller;

			#interrupt-cells = <2>;

			clocks = <&pclk>;

			clock-names = "apb_pclk";

		};



		gpio7: gpio@80d000 {

			compatible = "arm,pl061", "arm,primecell";

			reg = <0x80d000 0x1000>;

			interrupts = <0 71 0x4>;

			gpio-controller;

			#gpio-cells = <2>;

			gpio-ranges = <	&pmx0 0 19 1 &pmx0 1 20 1 &pmx0 2 21 1

					&pmx0 3 22 1 &pmx0 4 23 1 &pmx0 5 24 1

					&pmx0 6 25 1 &pmx0 7 26 1>;

			interrupt-controller;

			#interrupt-cells = <2>;

			clocks = <&pclk>;

			clock-names = "apb_pclk";

		};



		gpio8: gpio@80e000 {

			compatible = "arm,pl061", "arm,primecell";

			reg = <0x80e000 0x1000>;

			interrupts = <0 72 0x4>;

			gpio-controller;

			#gpio-cells = <2>;

			gpio-ranges = <	&pmx0 0 27 1 &pmx0 1 28 1 &pmx0 2 29 1

					&pmx0 3 30 1 &pmx0 4 31 1 &pmx0 5 32 1

					&pmx0 6 33 1 &pmx0 7 34 1>;

			interrupt-controller;

			#interrupt-cells = <2>;

			clocks = <&pclk>;

			clock-names = "apb_pclk";

		};



		gpio9: gpio@80f000 {

			compatible = "arm,pl061", "arm,primecell";

			reg = <0x80f000 0x1000>;

			interrupts = <0 73 0x4>;

			gpio-controller;

			#gpio-cells = <2>;

			gpio-ranges = <	&pmx0 0 35 1 &pmx0 1 36 1 &pmx0 2 37 1

					&pmx0 3 38 1 &pmx0 4 39 1 &pmx0 5 40 1

					&pmx0 6 41 1>;

			interrupt-controller;

			#interrupt-cells = <2>;

			clocks = <&pclk>;

			clock-names = "apb_pclk";

		};



		gpio10: gpio@810000 {

			compatible = "arm,pl061", "arm,primecell";

			reg = <0x810000 0x1000>;

			interrupts = <0 74 0x4>;

			gpio-controller;

			#gpio-cells = <2>;

			gpio-ranges = <	&pmx0 2 43 1 &pmx0 3 44 1 &pmx0 4 45 1

					&pmx0 5 45 1 &pmx0 6 46 1 &pmx0 7 46 1>;

			interrupt-controller;

			#interrupt-cells = <2>;

			clocks = <&pclk>;

			clock-names = "apb_pclk";

		};



		gpio11: gpio@811000 {

			compatible = "arm,pl061", "arm,primecell";

			reg = <0x811000 0x1000>;

			interrupts = <0 75 0x4>;

			gpio-controller;

			#gpio-cells = <2>;

			gpio-ranges = <	&pmx0 0 47 1 &pmx0 1 47 1 &pmx0 2 47 1

					&pmx0 3 47 1 &pmx0 4 47 1 &pmx0 5 48 1

					&pmx0 6 49 1 &pmx0 7 49 1>;

			interrupt-controller;

			#interrupt-cells = <2>;

			clocks = <&pclk>;

			clock-names = "apb_pclk";

		};



		gpio12: gpio@812000 {

			compatible = "arm,pl061", "arm,primecell";

			reg = <0x812000 0x1000>;

			interrupts = <0 76 0x4>;

			gpio-controller;

			#gpio-cells = <2>;

			gpio-ranges = <	&pmx0 0 49 1 &pmx0 1 50 1 &pmx0 2 49 1

					&pmx0 3 49 1 &pmx0 4 51 1 &pmx0 5 51 1

					&pmx0 6 51 1 &pmx0 7 52 1>;

			interrupt-controller;

			#interrupt-cells = <2>;

			clocks = <&pclk>;

			clock-names = "apb_pclk";

		};



		gpio13: gpio@813000 {

			compatible = "arm,pl061", "arm,primecell";

			reg = <0x813000 0x1000>;

			interrupts = <0 77 0x4>;

			gpio-controller;

			#gpio-cells = <2>;

			gpio-ranges = <	&pmx0 0 51 1 &pmx0 1 51 1 &pmx0 2 53 1

					&pmx0 3 53 1 &pmx0 4 53 1 &pmx0 5 54 1

					&pmx0 6 55 1 &pmx0 7 56 1>;

			interrupt-controller;

			#interrupt-cells = <2>;

			clocks = <&pclk>;

			clock-names = "apb_pclk";

		};



		gpio14: gpio@814000 {

			compatible = "arm,pl061", "arm,primecell";

			reg = <0x814000 0x1000>;

			interrupts = <0 78 0x4>;

			gpio-controller;

			#gpio-cells = <2>;

			gpio-ranges = <	&pmx0 0 57 1 &pmx0 1 97 1 &pmx0 2 97 1

					&pmx0 3 58 1 &pmx0 4 59 1 &pmx0 5 60 1

					&pmx0 6 60 1 &pmx0 7 61 1>;

			interrupt-controller;

			#interrupt-cells = <2>;

			clocks = <&pclk>;

			clock-names = "apb_pclk";

		};



		gpio15: gpio@815000 {

			compatible = "arm,pl061", "arm,primecell";

			reg = <0x815000 0x1000>;

			interrupts = <0 79 0x4>;

			gpio-controller;

			#gpio-cells = <2>;

			gpio-ranges = <	&pmx0 0 61 1 &pmx0 1 62 1 &pmx0 2 62 1

					&pmx0 3 63 1 &pmx0 4 63 1 &pmx0 5 64 1

					&pmx0 6 64 1 &pmx0 7 65 1>;

			interrupt-controller;

			#interrupt-cells = <2>;

			clocks = <&pclk>;

			clock-names = "apb_pclk";

		};



		gpio16: gpio@816000 {

			compatible = "arm,pl061", "arm,primecell";

			reg = <0x816000 0x1000>;

			interrupts = <0 80 0x4>;

			gpio-controller;

			#gpio-cells = <2>;

			gpio-ranges = <	&pmx0 0 66 1 &pmx0 1 67 1 &pmx0 2 68 1

					&pmx0 3 69 1 &pmx0 4 70 1 &pmx0 5 71 1

					&pmx0 6 72 1 &pmx0 7 73 1>;

			interrupt-controller;

			#interrupt-cells = <2>;

			clocks = <&pclk>;

			clock-names = "apb_pclk";

		};



		gpio17: gpio@817000 {

			compatible = "arm,pl061", "arm,primecell";

			reg = <0x817000 0x1000>;

			interrupts = <0 81 0x4>;

			gpio-controller;

			#gpio-cells = <2>;

			gpio-ranges = <	&pmx0 0 74 1 &pmx0 1 75 1 &pmx0 2 76 1

					&pmx0 3 77 1 &pmx0 4 78 1 &pmx0 5 79 1

					&pmx0 6 80 1 &pmx0 7 81 1>;

			interrupt-controller;

			#interrupt-cells = <2>;

			clocks = <&pclk>;

			clock-names = "apb_pclk";

		};



		gpio18: gpio@818000 {

			compatible = "arm,pl061", "arm,primecell";

			reg = <0x818000 0x1000>;

			interrupts = <0 82 0x4>;

			gpio-controller;

			#gpio-cells = <2>;

			gpio-ranges = <	&pmx0 0 82 1 &pmx0 1 83 1 &pmx0 2 83 1

					&pmx0 3 84 1 &pmx0 4 84 1 &pmx0 5 85 1

					&pmx0 6 86 1 &pmx0 7 87 1>;

			interrupt-controller;

			#interrupt-cells = <2>;

			clocks = <&pclk>;

			clock-names = "apb_pclk";

		};



		gpio19: gpio@819000 {

			compatible = "arm,pl061", "arm,primecell";

			reg = <0x819000 0x1000>;

			interrupts = <0 83 0x4>;

			gpio-controller;

			#gpio-cells = <2>;

			gpio-ranges = <	&pmx0 0 87 1 &pmx0 1 87 1 &pmx0 2 88 1

					&pmx0 3 88 1>;

			interrupt-controller;

			#interrupt-cells = <2>;

			clocks = <&pclk>;

			clock-names = "apb_pclk";

		};



		gpio20: gpio@81a000 {

			compatible = "arm,pl061", "arm,primecell";

			reg = <0x81a000 0x1000>;

			interrupts = <0 84 0x4>;

			gpio-controller;

			#gpio-cells = <2>;

			gpio-ranges = <	&pmx0 0 89 1 &pmx0 1 89 1 &pmx0 2 90 1

					&pmx0 3 90 1 &pmx0 4 91 1 &pmx0 5 92 1>;

			interrupt-controller;

			#interrupt-cells = <2>;

			clocks = <&pclk>;

			clock-names = "apb_pclk";

		};



		gpio21: gpio@81b000 {

			compatible = "arm,pl061", "arm,primecell";

			reg = <0x81b000 0x1000>;

			interrupts = <0 85 0x4>;

			gpio-controller;

			#gpio-cells = <2>;

			gpio-ranges = <	&pmx0 3 94 1 &pmx0 7 96 1>;

			interrupt-controller;

			#interrupt-cells = <2>;

			clocks = <&pclk>;

			clock-names = "apb_pclk";

		};



		pmx0: pinmux@803000 {

			compatible = "pinctrl-single";

			reg = <0x803000 0x188>;

			#address-cells = <1>;

			#size-cells = <1>;

			#gpio-range-cells = <3>;

			ranges;



			pinctrl-single,register-width = <32>;

			pinctrl-single,function-mask = <7>;

			/* pin base, nr pins & gpio function */

			pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1

						&range 12 1 0 &range 13 29 1

						&range 43 1 0 &range 44 49 1

						&range 94 1 1 &range 96 2 1>;



			range: gpio-range {

				#pinctrl-single,gpio-range-cells = <3>;

			};

		};



		pmx1: pinmux@803800 {

			compatible = "pinconf-single";

			reg = <0x803800 0x2dc>;

			#address-cells = <1>;

			#size-cells = <1>;

			ranges;



			pinctrl-single,register-width = <32>;

		};

	};

};

arch/arm/boot/dts/hi4511.dts

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