dt-bindings: clk: meson: add ao controller clock inputs

	- GXM (S912) : "amlogic,meson-gxm-aoclkc"

	- AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc"

	followed by the common "amlogic,meson-gx-aoclkc"

- clocks: list of clock phandle, one for each entry clock-names.

- clock-names: should contain the following:

  * "xtal"     : the platform xtal

  * "mpeg-clk" : the main clock controller mother clock (aka clk81)

  * "ext-32k-0"  : external 32kHz reference #0 if any (optional)

  * "ext-32k-1"  : external 32kHz reference #1 if any (optional - gx only)

  * "ext-32k-2"  : external 32kHz reference #2 if any (optional - gx only)

- #clock-cells: should be 1.

		compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};

		clocks = <&xtal>, <&clkc CLKID_CLK81>;

		clock-names = "xtal", "mpeg-clk";

	};

Example: UART controller node that consumes the clock and reset generated