clk: mediatek: add pericfg clocks for MT8183 (f9e55ac2) · Commits · 戴 / test

drivers/clk/mediatek/clk-mt8183.c

+30 −0

Original line number	Diff line number	Diff line
		@@ -1002,6 +1002,20 @@ static const struct mtk_gate infra_clks[] = {
		"msdc50_0_sel", 24),
		};

		static const struct mtk_gate_regs peri_cg_regs = {
		.set_ofs = 0x20c,
		.clr_ofs = 0x20c,
		.sta_ofs = 0x20c,
		};

		#define GATE_PERI(_id, _name, _parent, _shift) \
		GATE_MTK(_id, _name, _parent, &peri_cg_regs, _shift, \
		&mtk_clk_gate_ops_no_setclr_inv)

		static const struct mtk_gate peri_clks[] = {
		GATE_PERI(CLK_PERI_AXI, "peri_axi", "axi_sel", 31),
		};

		static const struct mtk_gate_regs apmixed_cg_regs = {
		.set_ofs = 0x20,
		.clr_ofs = 0x20,
		@@ -1208,6 +1222,19 @@ static int clk_mt8183_infra_probe(struct platform_device *pdev)
		return r;
		}

		static int clk_mt8183_peri_probe(struct platform_device *pdev)
		{
		struct clk_onecell_data *clk_data;
		struct device_node *node = pdev->dev.of_node;

		clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);

		mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
		clk_data);

		return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
		}

		static int clk_mt8183_mcu_probe(struct platform_device *pdev)
		{
		struct clk_onecell_data *clk_data;
		@@ -1237,6 +1264,9 @@ static const struct of_device_id of_match_clk_mt8183[] = {
		}, {
		.compatible = "mediatek,mt8183-infracfg",
		.data = clk_mt8183_infra_probe,
		}, {
		.compatible = "mediatek,mt8183-pericfg",
		.data = clk_mt8183_peri_probe,
		}, {
		.compatible = "mediatek,mt8183-mcucfg",
		.data = clk_mt8183_mcu_probe,

+4 −0