Commit f9ae487e authored by Thor Thayer's avatar Thor Thayer Committed by Borislav Petkov
Browse files

EDAC, altera: Generalize driver to use DT Memory size 



The Arria10 SOC uses a completely different SDRAM controller from the
earlier CycloneV and ArriaV SoCs. The memory size is calculated in the
bootloader and passed via the device tree. Using this device tree size
is more generic than using the register fields to calculate the memory
size for different SDRAM controllers.

Signed-off-by: default avatarThor Thayer <tthayer@opensource.altera.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: devicetree@vger.kernel.org
Cc: dinguyen@opensource.altera.com
Cc: galak@codeaurora.org
Cc: grant.likely@linaro.org
Cc: ijc+devicetree@hellion.org.uk
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: m.chehab@samsung.com
Cc: mark.rutland@arm.com
Cc: pawel.moll@arm.com
Cc: robh+dt@kernel.org
Cc: tthayer.linux@gmail.com
Link: http://lkml.kernel.org/r/1433428128-7292-2-git-send-email-tthayer@opensource.altera.com


Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
parent 99e21fea

drivers/edac/altera_edac.c

+26 −32
Original line number Diff line number Diff line
@@ -219,36 +219,31 @@ static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info *mci) 
{}

#endif



/* Get total memory size in bytes */

static u32 altr_sdram_get_total_mem_size(struct regmap *mc_vbase)

/* Get total memory size from Open Firmware DTB */

static unsigned long get_total_mem(void)

{

	u32 size, read_reg, row, bank, col, cs, width;



	if (regmap_read(mc_vbase, DRAMADDRW_OFST, &read_reg) < 0)

		return 0;



	if (regmap_read(mc_vbase, DRAMIFWIDTH_OFST, &width) < 0)

		return 0;



	col = (read_reg & DRAMADDRW_COLBIT_MASK) >>

		DRAMADDRW_COLBIT_SHIFT;

	row = (read_reg & DRAMADDRW_ROWBIT_MASK) >>

		DRAMADDRW_ROWBIT_SHIFT;

	bank = (read_reg & DRAMADDRW_BANKBIT_MASK) >>

		DRAMADDRW_BANKBIT_SHIFT;

	cs = (read_reg & DRAMADDRW_CSBIT_MASK) >>

		DRAMADDRW_CSBIT_SHIFT;



	/* Correct for ECC as its not addressible */

	if (width == DRAMIFWIDTH_32B_ECC)

		width = 32;

	if (width == DRAMIFWIDTH_16B_ECC)

		width = 16;



	/* calculate the SDRAM size base on this info */

	size = 1 << (row + bank + col);

	size = size * cs * (width / 8);

	return size;

	struct device_node *np = NULL;

	const unsigned int *reg, *reg_end;

	int len, sw, aw;

	unsigned long start, size, total_mem = 0;



	for_each_node_by_type(np, "memory") {

		aw = of_n_addr_cells(np);

		sw = of_n_size_cells(np);

		reg = (const unsigned int *)of_get_property(np, "reg", &len);

		reg_end = reg + (len / sizeof(u32));



		total_mem = 0;

		do {

			start = of_read_number(reg, aw);

			reg += aw;

			size = of_read_number(reg, sw);

			reg += sw;

			total_mem += size;

		} while (reg < reg_end);

	}

	edac_dbg(0, "total_mem 0x%lx\n", total_mem);

	return total_mem;

}



static int altr_sdram_probe(struct platform_device *pdev)
@@ -280,10 +275,9 @@ static int altr_sdram_probe(struct platform_device *pdev) 
	}



	/* Grab memory size from device tree. */

	mem_size = altr_sdram_get_total_mem_size(mc_vbase);

	mem_size = get_total_mem();

	if (!mem_size) {

		edac_printk(KERN_ERR, EDAC_MC,

			    "Unable to calculate memory size\n");

		edac_printk(KERN_ERR, EDAC_MC, "Unable to calculate memory size\n");

		return -ENODEV;

	}

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