Commit f998dc45 authored by Grygorii Strashko's avatar Grygorii Strashko Committed by David S. Miller
Browse files

arm64: dts: ti: k3-j721e-common-proc-board: add mcu cpsw nuss pinmux and phy defs 



The TI J721E EVM base board has TI DP83867 PHY connected to external CPSW
NUSS Port 1 in rgmii-rxid mode.

Hence, add pinmux and Ethernet PHY configuration for TI j721e SoC MCU
Gigabit Ethernet two ports Switch subsystem (CPSW NUSS).

Signed-off-by: default avatarGrygorii Strashko <grygorii.strashko@ti.com>
Tested-by: default avatarMurali Karicheri <m-karicheri2@ti.com>
Tested-by: default avatarPeter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent ae7fdac8

arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts

+43 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ 
#include "k3-j721e-som-p0.dtsi"

#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/input/input.h>

#include <dt-bindings/net/ti-dp83867.h>



/ {

	chosen {
@@ -128,6 +129,30 @@ 
			J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */

		>;

	};



	mcu_cpsw_pins_default: mcu_cpsw_pins_default {

		pinctrl-single,pins = <

			J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */

			J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */

			J721E_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */

			J721E_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */

			J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */

			J721E_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */

			J721E_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */

			J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */

			J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */

			J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */

			J721E_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* MCU_RGMII1_TXC */

			J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* MCU_RGMII1_RXC */

		>;

	};



	mcu_mdio_pins_default: mcu_mdio1_pins_default {

		pinctrl-single,pins = <

			J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* MCU_MDIO0_MDC */

			J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_MDIO0_MDIO */

		>;

	};

};



&wkup_uart0 {
@@ -429,3 +454,21 @@ 
		#gpio-cells = <2>;

	};

};



&mcu_cpsw {

	pinctrl-names = "default";

	pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;

};



&davinci_mdio {

	phy0: ethernet-phy@0 {

		reg = <0>;

		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;

		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;

	};

};



&cpsw_port1 {

	phy-mode = "rgmii-rxid";

	phy-handle = <&phy0>;

};

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