ARM: AM43xx: clk: Change the cpts ref clock source to dpll_core_m5 clk

int __init am43xx_dt_clk_init(void)

{

	struct clk *clk1, *clk2;

	ti_dt_clocks_register(am43xx_clks);

	omap2_clk_disable_autoidle_all();

	/*

	 * cpsw_cpts_rft_clk  has got the choice of 3 clocksources

	 * dpll_core_m4_ck, dpll_core_m5_ck and dpll_disp_m2_ck.

	 * By default dpll_core_m4_ck is selected, witn this as clock

	 * source the CPTS doesnot work properly. It gives clockcheck errors

	 * while running PTP.

	 * clockcheck: clock jumped backward or running slower than expected!

	 * By selecting dpll_core_m5_ck as the clocksource fixes this issue.

	 * In AM335x dpll_core_m5_ck is the default clocksource.

	 */

	clk1 = clk_get_sys(NULL, "cpsw_cpts_rft_clk");

	clk2 = clk_get_sys(NULL, "dpll_core_m5_ck");

	clk_set_parent(clk1, clk2);

	return 0;

}