Commit f932449c authored by Paul Cercueil's avatar Paul Cercueil Committed by Thomas Bogendoerfer
Browse files

MIPS: ingenic: Drop obsolete code, merge the rest in setup.c 



Drop a bootload of 10-years-old dirty code, that is not used anymore, as
it has been replaced with clean code over the ages.

Merge the very few bits left inside setup.c, so that everything is clean
and tidy now.

Signed-off-by: default avatarPaul Cercueil <paul@crapouillou.net>
Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent 8827af94

arch/mips/include/asm/mach-jz4740/base.h

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/* SPDX-License-Identifier: GPL-2.0 */

#ifndef __ASM_MACH_JZ4740_BASE_H__

#define __ASM_MACH_JZ4740_BASE_H__



#define JZ4740_CPM_BASE_ADDR	0x10000000

#define JZ4740_INTC_BASE_ADDR	0x10001000

#define JZ4740_WDT_BASE_ADDR	0x10002000

#define JZ4740_TCU_BASE_ADDR	0x10002010

#define JZ4740_RTC_BASE_ADDR	0x10003000

#define JZ4740_GPIO_BASE_ADDR	0x10010000

#define JZ4740_AIC_BASE_ADDR	0x10020000

#define JZ4740_MSC_BASE_ADDR	0x10021000

#define JZ4740_UART0_BASE_ADDR	0x10030000

#define JZ4740_UART1_BASE_ADDR	0x10031000

#define JZ4740_I2C_BASE_ADDR	0x10042000

#define JZ4740_SSI_BASE_ADDR	0x10043000

#define JZ4740_SADC_BASE_ADDR	0x10070000

#define JZ4740_EMC_BASE_ADDR	0x13010000

#define JZ4740_DMAC_BASE_ADDR	0x13020000

#define JZ4740_UHC_BASE_ADDR	0x13030000

#define JZ4740_UDC_BASE_ADDR	0x13040000

#define JZ4740_LCD_BASE_ADDR	0x13050000

#define JZ4740_SLCD_BASE_ADDR	0x13050000

#define JZ4740_CIM_BASE_ADDR	0x13060000

#define JZ4740_IPU_BASE_ADDR	0x13080000



#endif

arch/mips/include/asm/mach-jz4740/dma.h

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/* SPDX-License-Identifier: GPL-2.0-or-later */

/*

 *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>

 *  JZ7420/JZ4740 DMA definitions

 */



#ifndef __ASM_MACH_JZ4740_DMA_H__

#define __ASM_MACH_JZ4740_DMA_H__



enum jz4740_dma_request_type {

	JZ4740_DMA_TYPE_AUTO_REQUEST	= 8,

	JZ4740_DMA_TYPE_UART_TRANSMIT	= 20,

	JZ4740_DMA_TYPE_UART_RECEIVE	= 21,

	JZ4740_DMA_TYPE_SPI_TRANSMIT	= 22,

	JZ4740_DMA_TYPE_SPI_RECEIVE	= 23,

	JZ4740_DMA_TYPE_MMC_TRANSMIT	= 26,

	JZ4740_DMA_TYPE_MMC_RECEIVE	= 27,

	JZ4740_DMA_TYPE_TCU		= 28,

	JZ4740_DMA_TYPE_SADC		= 29,

	JZ4740_DMA_TYPE_SLCD		= 30,

};



#endif	/* __ASM_JZ4740_DMA_H__ */

arch/mips/include/asm/mach-jz4740/irq.h

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@@ -8,49 +8,6 @@ 
#define __ASM_MACH_JZ4740_IRQ_H__



#define MIPS_CPU_IRQ_BASE 0

#define JZ4740_IRQ_BASE 8



#ifdef CONFIG_MACH_JZ4740

# define NR_INTC_IRQS	32

#else

# define NR_INTC_IRQS	64

#endif



/* 1st-level interrupts */

#define JZ4740_IRQ(x)		(JZ4740_IRQ_BASE + (x))

#define JZ4740_IRQ_I2C		JZ4740_IRQ(1)

#define JZ4740_IRQ_UHC		JZ4740_IRQ(3)

#define JZ4740_IRQ_UART1	JZ4740_IRQ(8)

#define JZ4740_IRQ_UART0	JZ4740_IRQ(9)

#define JZ4740_IRQ_SADC		JZ4740_IRQ(12)

#define JZ4740_IRQ_MSC		JZ4740_IRQ(14)

#define JZ4740_IRQ_RTC		JZ4740_IRQ(15)

#define JZ4740_IRQ_SSI		JZ4740_IRQ(16)

#define JZ4740_IRQ_CIM		JZ4740_IRQ(17)

#define JZ4740_IRQ_AIC		JZ4740_IRQ(18)

#define JZ4740_IRQ_ETH		JZ4740_IRQ(19)

#define JZ4740_IRQ_DMAC		JZ4740_IRQ(20)

#define JZ4740_IRQ_TCU2		JZ4740_IRQ(21)

#define JZ4740_IRQ_TCU1		JZ4740_IRQ(22)

#define JZ4740_IRQ_TCU0		JZ4740_IRQ(23)

#define JZ4740_IRQ_UDC		JZ4740_IRQ(24)

#define JZ4740_IRQ_GPIO3	JZ4740_IRQ(25)

#define JZ4740_IRQ_GPIO2	JZ4740_IRQ(26)

#define JZ4740_IRQ_GPIO1	JZ4740_IRQ(27)

#define JZ4740_IRQ_GPIO0	JZ4740_IRQ(28)

#define JZ4740_IRQ_IPU		JZ4740_IRQ(29)

#define JZ4740_IRQ_LCD		JZ4740_IRQ(30)



#define JZ4780_IRQ_TCU2		JZ4740_IRQ(25)



/* 2nd-level interrupts */

#define JZ4740_IRQ_DMA(x)	(JZ4740_IRQ(NR_INTC_IRQS) + (x))



#define JZ4740_IRQ_INTC_GPIO(x) (JZ4740_IRQ_GPIO0 - (x))

#define JZ4740_IRQ_GPIO(x)	(JZ4740_IRQ(NR_INTC_IRQS + 16) + (x))



#define JZ4740_IRQ_ADC_BASE	JZ4740_IRQ(NR_INTC_IRQS + 144)



#define NR_IRQS (JZ4740_IRQ_ADC_BASE + 6)

#define NR_IRQS 256



#endif

arch/mips/include/asm/mach-jz4740/timer.h

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+0 −126
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-or-later */

/*

 *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>

 *  JZ4740 platform timer support

 */



#ifndef __ASM_MACH_JZ4740_TIMER

#define __ASM_MACH_JZ4740_TIMER



#define JZ_REG_TIMER_STOP		0x0C

#define JZ_REG_TIMER_STOP_SET		0x1C

#define JZ_REG_TIMER_STOP_CLEAR		0x2C

#define JZ_REG_TIMER_ENABLE		0x00

#define JZ_REG_TIMER_ENABLE_SET		0x04

#define JZ_REG_TIMER_ENABLE_CLEAR	0x08

#define JZ_REG_TIMER_FLAG		0x10

#define JZ_REG_TIMER_FLAG_SET		0x14

#define JZ_REG_TIMER_FLAG_CLEAR		0x18

#define JZ_REG_TIMER_MASK		0x20

#define JZ_REG_TIMER_MASK_SET		0x24

#define JZ_REG_TIMER_MASK_CLEAR		0x28



#define JZ_REG_TIMER_DFR(x) (((x) * 0x10) + 0x30)

#define JZ_REG_TIMER_DHR(x) (((x) * 0x10) + 0x34)

#define JZ_REG_TIMER_CNT(x) (((x) * 0x10) + 0x38)

#define JZ_REG_TIMER_CTRL(x) (((x) * 0x10) + 0x3C)



#define JZ_TIMER_IRQ_HALF(x) BIT((x) + 0x10)

#define JZ_TIMER_IRQ_FULL(x) BIT(x)



#define JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN	BIT(9)

#define JZ_TIMER_CTRL_PWM_ACTIVE_LOW		BIT(8)

#define JZ_TIMER_CTRL_PWM_ENABLE		BIT(7)

#define JZ_TIMER_CTRL_PRESCALE_MASK		0x1c

#define JZ_TIMER_CTRL_PRESCALE_OFFSET		0x3

#define JZ_TIMER_CTRL_PRESCALE_1		(0 << 3)

#define JZ_TIMER_CTRL_PRESCALE_4		(1 << 3)

#define JZ_TIMER_CTRL_PRESCALE_16		(2 << 3)

#define JZ_TIMER_CTRL_PRESCALE_64		(3 << 3)

#define JZ_TIMER_CTRL_PRESCALE_256		(4 << 3)

#define JZ_TIMER_CTRL_PRESCALE_1024		(5 << 3)



#define JZ_TIMER_CTRL_PRESCALER(x) ((x) << JZ_TIMER_CTRL_PRESCALE_OFFSET)



#define JZ_TIMER_CTRL_SRC_EXT		BIT(2)

#define JZ_TIMER_CTRL_SRC_RTC		BIT(1)

#define JZ_TIMER_CTRL_SRC_PCLK		BIT(0)



extern void __iomem *jz4740_timer_base;

void __init jz4740_timer_init(void);



void jz4740_timer_enable_watchdog(void);

void jz4740_timer_disable_watchdog(void);



static inline void jz4740_timer_stop(unsigned int timer)

{

	writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);

}



static inline void jz4740_timer_start(unsigned int timer)

{

	writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);

}



static inline bool jz4740_timer_is_enabled(unsigned int timer)

{

	return readb(jz4740_timer_base + JZ_REG_TIMER_ENABLE) & BIT(timer);

}



static inline void jz4740_timer_enable(unsigned int timer)

{

	writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_SET);

}



static inline void jz4740_timer_disable(unsigned int timer)

{

	writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_CLEAR);

}



static inline void jz4740_timer_set_period(unsigned int timer, uint16_t period)

{

	writew(period, jz4740_timer_base + JZ_REG_TIMER_DFR(timer));

}



static inline void jz4740_timer_set_duty(unsigned int timer, uint16_t duty)

{

	writew(duty, jz4740_timer_base + JZ_REG_TIMER_DHR(timer));

}



static inline void jz4740_timer_set_count(unsigned int timer, uint16_t count)

{

	writew(count, jz4740_timer_base + JZ_REG_TIMER_CNT(timer));

}



static inline uint16_t jz4740_timer_get_count(unsigned int timer)

{

	return readw(jz4740_timer_base + JZ_REG_TIMER_CNT(timer));

}



static inline void jz4740_timer_ack_full(unsigned int timer)

{

	writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);

}



static inline void jz4740_timer_irq_full_enable(unsigned int timer)

{

	writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);

	writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_CLEAR);

}



static inline void jz4740_timer_irq_full_disable(unsigned int timer)

{

	writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_SET);

}



static inline void jz4740_timer_set_ctrl(unsigned int timer, uint16_t ctrl)

{

	writew(ctrl, jz4740_timer_base + JZ_REG_TIMER_CTRL(timer));

}



static inline uint16_t jz4740_timer_get_ctrl(unsigned int timer)

{

	return readw(jz4740_timer_base + JZ_REG_TIMER_CTRL(timer));

}



#endif

arch/mips/jz4740/Makefile

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@@ -4,11 +4,6 @@ 
#



# Object file lists.



obj-y += prom.o time.o reset.o setup.o timer.o

obj-y += setup.o



CFLAGS_setup.o = -I$(src)/../../../scripts/dtc/libfdt
 


# PM support



obj-$(CONFIG_PM) += pm.o

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