Commit f92a6b08 authored by David Daney's avatar David Daney Committed by Ralf Baechle
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MIPS: Octeon: Enable Read Inhibit / eXecute Inhibit on Octeon II.

parent 0e56b385
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+1 −1
Original line number Diff line number Diff line
@@ -59,7 +59,7 @@
#define cpu_has_veic		0
#define cpu_hwrena_impl_bits	0xc0000000

#define kernel_uses_smartmips_rixi (cpu_data[0].cputype == CPU_CAVIUM_OCTEON_PLUS)
#define kernel_uses_smartmips_rixi (cpu_data[0].cputype != CPU_CAVIUM_OCTEON)

#define ARCH_HAS_IRQ_PER_CPU	1
#define ARCH_HAS_SPINLOCK_PREFETCH 1