Commit f9234633 authored by Matthijs Kooijman's avatar Matthijs Kooijman Committed by Greg Kroah-Hartman
Browse files

staging: dwc2: unshift non-bool register value constants 



Various register fields wider than one bit have constants defined for
their value. Previously, these registers would define the values as they
appear in the register, so shifted to the right to the position the
value appears in the register.

This commit changes those constants to their natural values (e.g, 0, 1,
2, etc.), as they are after shifting the register value to the right.
This also changes all relevant code to shift the values before comparing
them with constants.

This has the advantage that the values can be stored in smaller
variables (now they always require a u32) and makes the handling of
these values more consistent with other register fields that represent
natural numbers instead of enumerations (e.g., number of host channels).

Signed-off-by: default avatarMatthijs Kooijman <matthijs@stdin.nl>
Acked-by: default avatarPaul Zimmerman <paulz@synopsys.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 3b9edf88

drivers/staging/dwc2/core.c

+33 −20
Original line number Diff line number Diff line
@@ -90,8 +90,10 @@ static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg) 
 */

static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)

{

	u32 hs_phy_type = hsotg->hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK;

	u32 fs_phy_type = hsotg->hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK;

	u32 hs_phy_type = (hsotg->hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >>

			  GHWCFG2_HS_PHY_TYPE_SHIFT;

	u32 fs_phy_type = (hsotg->hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >>

			  GHWCFG2_FS_PHY_TYPE_SHIFT;

	u32 hcfg, val;



	if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
@@ -108,7 +110,7 @@ static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg) 
	dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);

	hcfg = readl(hsotg->regs + HCFG);

	hcfg &= ~HCFG_FSLSPCLKSEL_MASK;

	hcfg |= val;

	hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT;

	writel(hcfg, hsotg->regs + HCFG);

}
@@ -256,8 +258,10 @@ static void dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 
		dwc2_hs_phy_init(hsotg, select_phy);

	}



	hs_phy_type = hsotg->hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK;

	fs_phy_type = hsotg->hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK;

	hs_phy_type = (hsotg->hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >>

		      GHWCFG2_HS_PHY_TYPE_SHIFT;

	fs_phy_type = (hsotg->hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >>

		      GHWCFG2_FS_PHY_TYPE_SHIFT;



	if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&

	    fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
@@ -279,7 +283,8 @@ static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg) 
{

	u32 ahbcfg = readl(hsotg->regs + GAHBCFG);



	switch (hsotg->hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) {

	switch ((hsotg->hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >>

		GHWCFG2_ARCHITECTURE_SHIFT) {

	case GHWCFG2_EXT_DMA_ARCH:

		dev_err(hsotg->dev, "External DMA Mode not supported\n");

		return -EINVAL;
@@ -328,7 +333,8 @@ static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg) 
	usbcfg = readl(hsotg->regs + GUSBCFG);

	usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP);



	switch (hsotg->hwcfg2 & GHWCFG2_OP_MODE_MASK) {

	switch ((hsotg->hwcfg2 & GHWCFG2_OP_MODE_MASK) >>

		GHWCFG2_OP_MODE_SHIFT) {

	case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:

		if (hsotg->core_params->otg_cap ==

				DWC2_CAP_PARAM_HNP_SRP_CAPABLE)
@@ -599,7 +605,8 @@ void dwc2_core_host_init(struct dwc2_hsotg *hsotg) 
	}



	if (hsotg->core_params->dma_desc_enable > 0) {

		u32 op_mode = hsotg->hwcfg2 & GHWCFG2_OP_MODE_MASK;

		u32 op_mode = (hsotg->hwcfg2 & GHWCFG2_OP_MODE_MASK) >>

			      GHWCFG2_OP_MODE_SHIFT;



		if (hsotg->snpsid < DWC2_CORE_REV_2_90a ||

		    !(hsotg->hwcfg4 & GHWCFG4_DESC_DMA) ||
@@ -1666,7 +1673,8 @@ u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg) 
	if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) &&

	    !(usbcfg & GUSBCFG_PHYIF16))

		clock = 60;

	if ((usbcfg & GUSBCFG_PHYSEL) && (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) ==

	if ((usbcfg & GUSBCFG_PHYSEL) &&

	    (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >> GHWCFG2_FS_PHY_TYPE_SHIFT ==

	    GHWCFG2_FS_PHY_TYPE_SHARED_ULPI)

		clock = 48;

	if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
@@ -1679,14 +1687,15 @@ u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg) 
	    !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))

		clock = 48;

	if ((usbcfg & GUSBCFG_PHYSEL) && !(usbcfg & GUSBCFG_PHYIF16) &&

	    (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) ==

	    (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >> GHWCFG2_FS_PHY_TYPE_SHIFT ==

	    GHWCFG2_FS_PHY_TYPE_SHARED_UTMI)

		clock = 48;

	if ((usbcfg & GUSBCFG_PHYSEL) && (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) ==

	if ((usbcfg & GUSBCFG_PHYSEL) &&

	    (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >> GHWCFG2_FS_PHY_TYPE_SHIFT ==

	    GHWCFG2_FS_PHY_TYPE_DEDICATED)

		clock = 48;



	if ((hprt0 & HPRT0_SPD_MASK) == HPRT0_SPD_HIGH_SPEED)

	if ((hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT == HPRT0_SPD_HIGH_SPEED)

		/* High speed case */

		return 125 * clock;

	else
@@ -1957,7 +1966,8 @@ int dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val) 
	int retval = 0;

	u32 op_mode;



	op_mode = hsotg->hwcfg2 & GHWCFG2_OP_MODE_MASK;

	op_mode = (hsotg->hwcfg2 & GHWCFG2_OP_MODE_MASK) >>

		  GHWCFG2_OP_MODE_SHIFT;



	switch (val) {

	case DWC2_CAP_PARAM_HNP_SRP_CAPABLE:
@@ -2015,8 +2025,8 @@ int dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val) 
	int valid = 1;

	int retval = 0;



	if (val > 0 && (hsotg->hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) ==

	    GHWCFG2_SLAVE_ONLY_ARCH)

	if (val > 0 && (hsotg->hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >>

		       GHWCFG2_ARCHITECTURE_SHIFT == GHWCFG2_SLAVE_ONLY_ARCH)

		valid = 0;

	if (val < 0)

		valid = 0;
@@ -2026,8 +2036,8 @@ int dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val) 
			dev_err(hsotg->dev,

				"%d invalid for dma_enable parameter. Check HW configuration.\n",

				val);

		val = (hsotg->hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) !=

			GHWCFG2_SLAVE_ONLY_ARCH;

		val = (hsotg->hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >>

		      GHWCFG2_ARCHITECTURE_SHIFT != GHWCFG2_SLAVE_ONLY_ARCH;

		dev_dbg(hsotg->dev, "Setting dma_enable to %d\n", val);

		retval = -EINVAL;

	}
@@ -2276,8 +2286,10 @@ int dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val) 
	}



#ifndef NO_FS_PHY_HW_CHECKS

	hs_phy_type = hsotg->hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK;

	fs_phy_type = hsotg->hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK;

	hs_phy_type = (hsotg->hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >>

		      GHWCFG2_HS_PHY_TYPE_SHIFT;

	fs_phy_type = (hsotg->hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >>

		      GHWCFG2_FS_PHY_TYPE_SHIFT;



	if (val == DWC2_PHY_TYPE_PARAM_UTMI &&

	    (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
@@ -2588,7 +2600,8 @@ int dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val) 
	if (val != -1)

		hsotg->core_params->ahbcfg = val;

	else

		hsotg->core_params->ahbcfg = GAHBCFG_HBSTLEN_INCR4;

		hsotg->core_params->ahbcfg = GAHBCFG_HBSTLEN_INCR4 <<

                                             GAHBCFG_HBSTLEN_SHIFT;

	return 0;

}

drivers/staging/dwc2/hcd.c

+1 −1
Original line number Diff line number Diff line
@@ -1612,7 +1612,7 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq, 
		if (hprt0 & HPRT0_PWR)

			port_status |= USB_PORT_STAT_POWER;



		speed = hprt0 & HPRT0_SPD_MASK;

		speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;

		if (speed == HPRT0_SPD_HIGH_SPEED)

			port_status |= USB_PORT_STAT_HIGH_SPEED;

		else if (speed == HPRT0_SPD_LOW_SPEED)

drivers/staging/dwc2/hcd.h

+9 −9
Original line number Diff line number Diff line
@@ -122,11 +122,11 @@ struct dwc2_host_chan { 
	unsigned ep_type:2;

	unsigned max_packet:11;

	unsigned data_pid_start:2;

#define DWC2_HC_PID_DATA0	(TSIZ_SC_MC_PID_DATA0 >> TSIZ_SC_MC_PID_SHIFT)

#define DWC2_HC_PID_DATA2	(TSIZ_SC_MC_PID_DATA2 >> TSIZ_SC_MC_PID_SHIFT)

#define DWC2_HC_PID_DATA1	(TSIZ_SC_MC_PID_DATA1 >> TSIZ_SC_MC_PID_SHIFT)

#define DWC2_HC_PID_MDATA	(TSIZ_SC_MC_PID_MDATA >> TSIZ_SC_MC_PID_SHIFT)

#define DWC2_HC_PID_SETUP	(TSIZ_SC_MC_PID_SETUP >> TSIZ_SC_MC_PID_SHIFT)

#define DWC2_HC_PID_DATA0	TSIZ_SC_MC_PID_DATA0

#define DWC2_HC_PID_DATA2	TSIZ_SC_MC_PID_DATA2

#define DWC2_HC_PID_DATA1	TSIZ_SC_MC_PID_DATA1

#define DWC2_HC_PID_MDATA	TSIZ_SC_MC_PID_MDATA

#define DWC2_HC_PID_SETUP	TSIZ_SC_MC_PID_SETUP



	unsigned multi_count:2;
@@ -146,10 +146,10 @@ struct dwc2_host_chan { 
	u8 hub_addr;

	u8 hub_port;

	u8 xact_pos;

#define DWC2_HCSPLT_XACTPOS_MID	(HCSPLT_XACTPOS_MID >> HCSPLT_XACTPOS_SHIFT)

#define DWC2_HCSPLT_XACTPOS_END	(HCSPLT_XACTPOS_END >> HCSPLT_XACTPOS_SHIFT)

#define DWC2_HCSPLT_XACTPOS_BEGIN (HCSPLT_XACTPOS_BEGIN >> HCSPLT_XACTPOS_SHIFT)

#define DWC2_HCSPLT_XACTPOS_ALL	(HCSPLT_XACTPOS_ALL >> HCSPLT_XACTPOS_SHIFT)

#define DWC2_HCSPLT_XACTPOS_MID	HCSPLT_XACTPOS_MID

#define DWC2_HCSPLT_XACTPOS_END	HCSPLT_XACTPOS_END

#define DWC2_HCSPLT_XACTPOS_BEGIN HCSPLT_XACTPOS_BEGIN

#define DWC2_HCSPLT_XACTPOS_ALL	HCSPLT_XACTPOS_ALL



	u8 requests;

	u8 schinfo;

drivers/staging/dwc2/hcd_intr.c

+10 −9
Original line number Diff line number Diff line
@@ -177,7 +177,7 @@ static void dwc2_rx_fifo_level_intr(struct dwc2_hsotg *hsotg) 
	       GRXSTS_BYTECNT_MASK >> GRXSTS_BYTECNT_SHIFT;

	dpid = grxsts >> GRXSTS_DPID_SHIFT &

	       GRXSTS_DPID_MASK >> GRXSTS_DPID_SHIFT;

	pktsts = grxsts & GRXSTS_PKTSTS_MASK;

	pktsts = (grxsts & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT;



	/* Packet Status */

	if (dbg_perio()) {
@@ -185,9 +185,7 @@ static void dwc2_rx_fifo_level_intr(struct dwc2_hsotg *hsotg) 
		dev_vdbg(hsotg->dev, "    Count = %d\n", bcnt);

		dev_vdbg(hsotg->dev, "    DPID = %d, chan.dpid = %d\n", dpid,

			 chan->data_pid_start);

		dev_vdbg(hsotg->dev, "    PStatus = %d\n",

			 pktsts >> GRXSTS_PKTSTS_SHIFT &

			 GRXSTS_PKTSTS_MASK >> GRXSTS_PKTSTS_SHIFT);

		dev_vdbg(hsotg->dev, "    PStatus = %d\n", pktsts);

	}



	switch (pktsts) {
@@ -266,7 +264,7 @@ static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0, 
	}



	usbcfg = readl(hsotg->regs + GUSBCFG);

	prtspd = hprt0 & HPRT0_SPD_MASK;

	prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;



	if (prtspd == HPRT0_SPD_LOW_SPEED || prtspd == HPRT0_SPD_FULL_SPEED) {

		/* Low power */
@@ -278,7 +276,8 @@ static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0, 
		}



		hcfg = readl(hsotg->regs + HCFG);

		fslspclksel = hcfg & HCFG_FSLSPCLKSEL_MASK;

		fslspclksel = (hcfg & HCFG_FSLSPCLKSEL_MASK) >>

			      HCFG_FSLSPCLKSEL_SHIFT;



		if (prtspd == HPRT0_SPD_LOW_SPEED &&

		    params->host_ls_low_power_phy_clk ==
@@ -287,8 +286,9 @@ static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0, 
			dev_vdbg(hsotg->dev,

				 "FS_PHY programming HCFG to 6 MHz\n");

			if (fslspclksel != HCFG_FSLSPCLKSEL_6_MHZ) {

				fslspclksel = HCFG_FSLSPCLKSEL_6_MHZ;

				hcfg &= ~HCFG_FSLSPCLKSEL_MASK;

				hcfg |= HCFG_FSLSPCLKSEL_6_MHZ;

				hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT;

				writel(hcfg, hsotg->regs + HCFG);

				do_reset = 1;

			}
@@ -297,8 +297,9 @@ static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0, 
			dev_vdbg(hsotg->dev,

				 "FS_PHY programming HCFG to 48 MHz\n");

			if (fslspclksel != HCFG_FSLSPCLKSEL_48_MHZ) {

				fslspclksel = HCFG_FSLSPCLKSEL_48_MHZ;

				hcfg &= ~HCFG_FSLSPCLKSEL_MASK;

				hcfg |= HCFG_FSLSPCLKSEL_48_MHZ;

				hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT;

				writel(hcfg, hsotg->regs + HCFG);

				do_reset = 1;

			}
@@ -515,7 +516,7 @@ void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg, 
			       struct dwc2_qtd *qtd)

{

	u32 hctsiz = readl(hsotg->regs + HCTSIZ(chnum));

	u32 pid = hctsiz & TSIZ_SC_MC_PID_MASK;

	u32 pid = (hctsiz & TSIZ_SC_MC_PID_MASK) >> TSIZ_SC_MC_PID_SHIFT;



	if (chan->ep_type != USB_ENDPOINT_XFER_CONTROL) {

		if (pid == TSIZ_SC_MC_PID_DATA0)

drivers/staging/dwc2/hcd_queue.c

+1 −1
Original line number Diff line number Diff line
@@ -116,7 +116,7 @@ static void dwc2_qh_init(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 
			qh->interval = 8;

#endif

		hprt = readl(hsotg->regs + HPRT0);

		prtspd = hprt & HPRT0_SPD_MASK;

		prtspd = (hprt & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;

		if (prtspd == HPRT0_SPD_HIGH_SPEED &&

		    (dev_speed == USB_SPEED_LOW ||

		     dev_speed == USB_SPEED_FULL)) {

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