ARM: l2c: tegra: remove cache size override (f9040550) · Commits · 戴 / test

The cache size should already be present in the L2 cache auxiliary control register: it is part of the integration process to configure the hardware IP. Most platforms get this right, yet still many cargo-cult program, and assume that they always need specifying to the L2 cache code. Remove them so we can find out which really need this. Acked-by:

Stephen Warren <swarren@nvidia.com> Tested-by:

Stephen Warren <swarren@nvidia.com> Acked-by:

Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by:

Russell King <rmk+kernel@arm.linux.org.uk>

arch/arm/mach-tegra/tegra.c

+1 −17

Original line number	Diff line number	Diff line
		@@ -73,25 +73,9 @@ u32 tegra_uart_config[3] = {
		static void __init tegra_init_cache(void)
		{
		#ifdef CONFIG_CACHE_L2X0
		static const struct of_device_id pl310_ids[] __initconst = {
		{ .compatible = "arm,pl310-cache", },
		{}
		};

		struct device_node *np;
		int ret;
		void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
		u32 aux_ctrl, cache_type;

		np = of_find_matching_node(NULL, pl310_ids);
		if (!np)
		return;

		cache_type = readl(p + L2X0_CACHE_TYPE);
		aux_ctrl = (cache_type & 0x700) << (17-8);
		aux_ctrl \|= 0x3c400001;

		ret = l2x0_of_init(aux_ctrl, 0xc200c3fe);
		ret = l2x0_of_init(0x3c400001, 0xc20fc3fe);
		if (!ret)
		l2x0_saved_regs_addr = virt_to_phys(&l2x0_saved_regs);
		#endif

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