MIPS: Octeon: Handle Octeon II caches. (f8bf7e68) · Commits · 戴 / test

arch/mips/mm/c-octeon.c

+15 −1

Original line number	Diff line number	Diff line
		@@ -181,10 +181,10 @@ static void __cpuinit probe_octeon(void)
		unsigned int config1;
		struct cpuinfo_mips *c = &current_cpu_data;

		config1 = read_c0_config1();
		switch (c->cputype) {
		case CPU_CAVIUM_OCTEON:
		case CPU_CAVIUM_OCTEON_PLUS:
		config1 = read_c0_config1();
		c->icache.linesz = 2 << ((config1 >> 19) & 7);
		c->icache.sets = 64 << ((config1 >> 22) & 7);
		c->icache.ways = 1 + ((config1 >> 16) & 7);
		@@ -204,6 +204,20 @@ static void __cpuinit probe_octeon(void)
		c->options \|= MIPS_CPU_PREFETCH;
		break;

		case CPU_CAVIUM_OCTEON2:
		c->icache.linesz = 2 << ((config1 >> 19) & 7);
		c->icache.sets = 8;
		c->icache.ways = 37;
		c->icache.flags \|= MIPS_CACHE_VTAG;
		icache_size = c->icache.sets * c->icache.ways * c->icache.linesz;

		c->dcache.linesz = 128;
		c->dcache.ways = 32;
		c->dcache.sets = 8;
		dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz;
		c->options \|= MIPS_CPU_PREFETCH;
		break;

		default:
		panic("Unsupported Cavium Networks CPU type\n");
		break;