Commit f8b58c64 authored by Christophe Leroy's avatar Christophe Leroy Committed by Michael Ellerman
Browse files

powerpc/603: let's handle PAGE_DIRTY directly 



PAGE_DIRTY corresponds to the C bit. If writing on
a page for which the C bit is not set, a DataStoreTLBMiss
is generated. No need to check it in DataLoadTLBMiss.

Signed-off-by: default avatarChristophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent 54a05a30

arch/powerpc/kernel/head_32.S

+2 −4
Original line number Diff line number Diff line
@@ -595,12 +595,10 @@ DataLoadTLBMiss: 
	stw	r0,0(r2)		/* update PTE (accessed bit) */

	/* Convert linux-style PTE to low word of PPC-style PTE */

	rlwinm	r1,r0,32-10,31,31	/* _PAGE_RW -> PP lsb */

	rlwinm	r2,r0,32-7,31,31	/* _PAGE_DIRTY -> PP lsb */

	and	r1,r1,r2		/* writable if _RW and _DIRTY */

	rlwimi	r0,r0,32-1,30,30	/* _PAGE_USER -> PP msb */

	rlwimi	r0,r0,32-1,31,31	/* _PAGE_USER -> PP lsb */

	ori	r1,r1,0xe04		/* clear out reserved bits */

	andc	r1,r0,r1		/* PP = user? (rw&dirty? 2: 3): 0 */

	andc	r1,r0,r1		/* PP = user? rw? 2: 3: 0 */

BEGIN_FTR_SECTION

	rlwinm	r1,r1,0,~_PAGE_COHERENT	/* clear M (coherence not required) */

END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
@@ -669,7 +667,7 @@ DataStoreTLBMiss: 
	lwz	r0,0(r2)		/* get linux-style pte */

	andc.	r1,r1,r0		/* check access & ~permission */

	bne-	DataAddressInvalid	/* return if access not permitted */

	ori	r0,r0,_PAGE_ACCESSED|_PAGE_DIRTY

	ori	r0,r0,_PAGE_ACCESSED

	/*

	 * NOTE! We are assuming this is not an SMP system, otherwise

	 * we would need to update the pte atomically with lwarx/stwcx.

CRA Git | Maintained and supported by SUSTech CRA and CCSE