Commit f899f786 authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: Move GGTT fence registers under gt/ 



Since the fence registers control HW detiling through the GGTT
aperture, make them a part of the intel_ggtt under gt/

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarMika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200316113846.4974-1-chris@chris-wilson.co.uk
parent a6277478

drivers/gpu/drm/i915/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -92,6 +92,7 @@ gt-y += \ 
	gt/intel_engine_pool.o \

	gt/intel_engine_user.o \

	gt/intel_ggtt.o \

	gt/intel_ggtt_fencing.o \

	gt/intel_gt.o \

	gt/intel_gt_irq.o \

	gt/intel_gt_pm.o \
@@ -153,7 +154,6 @@ i915-y += \ 
	  i915_buddy.o \

	  i915_cmd_parser.o \

	  i915_gem_evict.o \

	  i915_gem_fence_reg.o \

	  i915_gem_gtt.o \

	  i915_gem.o \

	  i915_globals.o \

drivers/gpu/drm/i915/gt/intel_ggtt.c

+1 −1
Original line number Diff line number Diff line
@@ -65,7 +65,7 @@ static int ggtt_init_hw(struct i915_ggtt *ggtt) 
					      ggtt->mappable_end);

	}



	i915_ggtt_init_fences(ggtt);

	intel_ggtt_init_fences(ggtt);



	return 0;

}

drivers/gpu/drm/i915/i915_gem_fence_reg.c→drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c

+10 −17
Original line number Diff line number Diff line
@@ -233,16 +233,9 @@ static int fence_update(struct i915_fence_reg *fence, 
	int ret;



	if (vma) {

		if (!i915_vma_is_map_and_fenceable(vma))

			return -EINVAL;



		if (drm_WARN(&uncore->i915->drm,

			     !i915_gem_object_get_stride(vma->obj) ||

			     !i915_gem_object_get_tiling(vma->obj),

			     "bogus fence setup with stride: 0x%x, tiling mode: %i\n",

			     i915_gem_object_get_stride(vma->obj),

			     i915_gem_object_get_tiling(vma->obj)))

			return -EINVAL;

		GEM_BUG_ON(!i915_vma_is_map_and_fenceable(vma));

		GEM_BUG_ON(!i915_gem_object_get_stride(vma->obj) ||

			   !i915_gem_object_get_tiling(vma->obj));



		ret = i915_vma_sync(vma);

		if (ret)
@@ -276,7 +269,7 @@ static int fence_update(struct i915_fence_reg *fence, 
	/*

	 * We only need to update the register itself if the device is awake.

	 * If the device is currently powered down, we will defer the write

	 * to the runtime resume, see i915_gem_restore_fences().

	 * to the runtime resume, see intel_ggtt_restore_fences().

	 *

	 * This only works for removing the fence register, on acquisition

	 * the caller must hold the rpm wakeref. The fence register must
@@ -487,14 +480,14 @@ void i915_unreserve_fence(struct i915_fence_reg *fence) 
}



/**

 * i915_gem_restore_fences - restore fence state

 * intel_ggtt_restore_fences - restore fence state

 * @ggtt: Global GTT

 *

 * Restore the hw fence state to match the software tracking again, to be called

 * after a gpu reset and on resume. Note that on runtime suspend we only cancel

 * the fences, to be reacquired by the user later.

 */

void i915_gem_restore_fences(struct i915_ggtt *ggtt)

void intel_ggtt_restore_fences(struct i915_ggtt *ggtt)

{

	int i;
@@ -746,7 +739,7 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt) 
 * bit 17 of its physical address and therefore being interpreted differently

 * by the GPU.

 */

static void i915_gem_swizzle_page(struct page *page)

static void swizzle_page(struct page *page)

{

	char temp[64];

	char *vaddr;
@@ -791,7 +784,7 @@ i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj, 
	for_each_sgt_page(page, sgt_iter, pages) {

		char new_bit_17 = page_to_phys(page) >> 17;

		if ((new_bit_17 & 0x1) != (test_bit(i, obj->bit_17) != 0)) {

			i915_gem_swizzle_page(page);

			swizzle_page(page);

			set_page_dirty(page);

		}

		i++;
@@ -836,7 +829,7 @@ i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj, 
	}

}



void i915_ggtt_init_fences(struct i915_ggtt *ggtt)

void intel_ggtt_init_fences(struct i915_ggtt *ggtt)

{

	struct drm_i915_private *i915 = ggtt->vm.i915;

	struct intel_uncore *uncore = ggtt->vm.gt->uncore;
@@ -875,7 +868,7 @@ void i915_ggtt_init_fences(struct i915_ggtt *ggtt) 
	}

	ggtt->num_fences = num_fences;



	i915_gem_restore_fences(ggtt);

	intel_ggtt_restore_fences(ggtt);

}



void intel_gt_init_swizzling(struct intel_gt *gt)

drivers/gpu/drm/i915/i915_gem_fence_reg.h→drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h

+4 −5
Original line number Diff line number Diff line
@@ -22,8 +22,8 @@ 
 *

 */



#ifndef __I915_FENCE_REG_H__

#define __I915_FENCE_REG_H__

#ifndef __INTEL_GGTT_FENCING_H__

#define __INTEL_GGTT_FENCING_H__



#include <linux/list.h>

#include <linux/types.h>
@@ -53,18 +53,17 @@ struct i915_fence_reg { 
	bool dirty;

};



/* i915_gem_fence_reg.c */

struct i915_fence_reg *i915_reserve_fence(struct i915_ggtt *ggtt);

void i915_unreserve_fence(struct i915_fence_reg *fence);



void i915_gem_restore_fences(struct i915_ggtt *ggtt);

void intel_ggtt_restore_fences(struct i915_ggtt *ggtt);



void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,

				       struct sg_table *pages);

void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,

					 struct sg_table *pages);



void i915_ggtt_init_fences(struct i915_ggtt *ggtt);

void intel_ggtt_init_fences(struct i915_ggtt *ggtt);



void intel_gt_init_swizzling(struct intel_gt *gt);

drivers/gpu/drm/i915/gt/intel_gtt.h

+1 −1
Original line number Diff line number Diff line
@@ -26,7 +26,7 @@ 
#include <drm/drm_mm.h>



#include "gt/intel_reset.h"

#include "i915_gem_fence_reg.h"

#include "gt/intel_ggtt_fencing.h"

#include "i915_selftest.h"

#include "i915_vma_types.h"

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