Merge branch '1GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/next-queue (f89370d4) · Commits · 戴 / test

drivers/net/ethernet/intel/e1000/e1000_main.c

+3 −1

Original line number	Diff line number	Diff line
		@@ -3136,8 +3136,9 @@ static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
		hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
		if (skb->data_len && hdr_len == len) {
		switch (hw->mac_type) {
		case e1000_82544: {
		unsigned int pull_size;
		case e1000_82544:

		/* Make sure we have room to chop off 4 bytes,
		* and that the end alignment will work out to
		* this hardware's requirements
		@@ -3158,6 +3159,7 @@ static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
		}
		len = skb_headlen(skb);
		break;
		}
		default:
		/* do nothing */
		break;

drivers/net/ethernet/intel/igc/Makefile

+1 −1

Original line number	Diff line number	Diff line
		@@ -8,4 +8,4 @@
		obj-$(CONFIG_IGC) += igc.o

		igc-objs := igc_main.o igc_mac.o igc_i225.o igc_base.o igc_nvm.o igc_phy.o \
		igc_ethtool.o igc_ptp.o igc_dump.o
		igc_ethtool.o igc_ptp.o igc_dump.o igc_tsn.o

drivers/net/ethernet/intel/igc/igc.h

+195 −194

Original line number	Diff line number	Diff line
		@@ -19,8 +19,199 @@
		/* forward declaration */
		void igc_set_ethtool_ops(struct net_device *);

		struct igc_adapter;
		struct igc_ring;
		/* Transmit and receive queues */
		#define IGC_MAX_RX_QUEUES 4
		#define IGC_MAX_TX_QUEUES 4

		#define MAX_Q_VECTORS 8
		#define MAX_STD_JUMBO_FRAME_SIZE 9216

		#define MAX_ETYPE_FILTER (4 - 1)
		#define IGC_RETA_SIZE 128

		struct igc_tx_queue_stats {
		u64 packets;
		u64 bytes;
		u64 restart_queue;
		u64 restart_queue2;
		};

		struct igc_rx_queue_stats {
		u64 packets;
		u64 bytes;
		u64 drops;
		u64 csum_err;
		u64 alloc_failed;
		};

		struct igc_rx_packet_stats {
		u64 ipv4_packets; /* IPv4 headers processed */
		u64 ipv4e_packets; /* IPv4E headers with extensions processed */
		u64 ipv6_packets; /* IPv6 headers processed */
		u64 ipv6e_packets; /* IPv6E headers with extensions processed */
		u64 tcp_packets; /* TCP headers processed */
		u64 udp_packets; /* UDP headers processed */
		u64 sctp_packets; /* SCTP headers processed */
		u64 nfs_packets; /* NFS headers processe */
		u64 other_packets;
		};

		struct igc_ring_container {
		struct igc_ring ring; / pointer to linked list of rings */
		unsigned int total_bytes; /* total bytes processed this int */
		unsigned int total_packets; /* total packets processed this int */
		u16 work_limit; /* total work allowed per interrupt */
		u8 count; /* total number of rings in vector */
		u8 itr; /* current ITR setting for ring */
		};

		struct igc_ring {
		struct igc_q_vector q_vector; / backlink to q_vector */
		struct net_device netdev; / back pointer to net_device */
		struct device dev; / device for dma mapping */
		union { /* array of buffer info structs */
		struct igc_tx_buffer *tx_buffer_info;
		struct igc_rx_buffer *rx_buffer_info;
		};
		void desc; / descriptor ring memory */
		unsigned long flags; /* ring specific flags */
		void __iomem tail; / pointer to ring tail register */
		dma_addr_t dma; /* phys address of the ring */
		unsigned int size; /* length of desc. ring in bytes */

		u16 count; /* number of desc. in the ring */
		u8 queue_index; /* logical index of the ring*/
		u8 reg_idx; /* physical index of the ring */
		bool launchtime_enable; /* true if LaunchTime is enabled */

		u32 start_time;
		u32 end_time;

		/* everything past this point are written often */
		u16 next_to_clean;
		u16 next_to_use;
		u16 next_to_alloc;

		union {
		/* TX */
		struct {
		struct igc_tx_queue_stats tx_stats;
		struct u64_stats_sync tx_syncp;
		struct u64_stats_sync tx_syncp2;
		};
		/* RX */
		struct {
		struct igc_rx_queue_stats rx_stats;
		struct igc_rx_packet_stats pkt_stats;
		struct u64_stats_sync rx_syncp;
		struct sk_buff *skb;
		};
		};
		} ____cacheline_internodealigned_in_smp;

		/* Board specific private data structure */
		struct igc_adapter {
		struct net_device *netdev;

		unsigned long state;
		unsigned int flags;
		unsigned int num_q_vectors;

		struct msix_entry *msix_entries;

		/* TX */
		u16 tx_work_limit;
		u32 tx_timeout_count;
		int num_tx_queues;
		struct igc_ring *tx_ring[IGC_MAX_TX_QUEUES];

		/* RX */
		int num_rx_queues;
		struct igc_ring *rx_ring[IGC_MAX_RX_QUEUES];

		struct timer_list watchdog_timer;
		struct timer_list dma_err_timer;
		struct timer_list phy_info_timer;

		u32 wol;
		u32 en_mng_pt;
		u16 link_speed;
		u16 link_duplex;

		u8 port_num;

		u8 __iomem *io_addr;
		/* Interrupt Throttle Rate */
		u32 rx_itr_setting;
		u32 tx_itr_setting;

		struct work_struct reset_task;
		struct work_struct watchdog_task;
		struct work_struct dma_err_task;
		bool fc_autoneg;

		u8 tx_timeout_factor;

		int msg_enable;
		u32 max_frame_size;
		u32 min_frame_size;

		ktime_t base_time;
		ktime_t cycle_time;

		/* OS defined structs */
		struct pci_dev *pdev;
		/* lock for statistics */
		spinlock_t stats64_lock;
		struct rtnl_link_stats64 stats64;

		/* structs defined in igc_hw.h */
		struct igc_hw hw;
		struct igc_hw_stats stats;

		struct igc_q_vector *q_vector[MAX_Q_VECTORS];
		u32 eims_enable_mask;
		u32 eims_other;

		u16 tx_ring_count;
		u16 rx_ring_count;

		u32 tx_hwtstamp_timeouts;
		u32 tx_hwtstamp_skipped;
		u32 rx_hwtstamp_cleared;

		u32 rss_queues;
		u32 rss_indir_tbl_init;

		/* RX network flow classification support */
		struct hlist_head nfc_filter_list;
		unsigned int nfc_filter_count;

		/* lock for RX network flow classification filter */
		spinlock_t nfc_lock;
		bool etype_bitmap[MAX_ETYPE_FILTER];

		struct igc_mac_addr *mac_table;

		u8 rss_indir_tbl[IGC_RETA_SIZE];

		unsigned long link_check_timeout;
		struct igc_info ei;

		struct ptp_clock *ptp_clock;
		struct ptp_clock_info ptp_caps;
		struct work_struct ptp_tx_work;
		struct sk_buff *ptp_tx_skb;
		struct hwtstamp_config tstamp_config;
		unsigned long ptp_tx_start;
		unsigned long last_rx_ptp_check;
		unsigned long last_rx_timestamp;
		unsigned int ptp_flags;
		/* System time value lock */
		spinlock_t tmreg_lock;
		struct cyclecounter cc;
		struct timecounter tc;
		};

		void igc_up(struct igc_adapter *adapter);
		void igc_down(struct igc_adapter *adapter);
		@@ -50,14 +241,10 @@ extern char igc_driver_name[];
		extern char igc_driver_version[];

		#define IGC_REGS_LEN 740
		#define IGC_RETA_SIZE 128

		/* flags controlling PTP/1588 function */
		#define IGC_PTP_ENABLED BIT(0)

		/* Interrupt defines */
		#define IGC_START_ITR 648 /* ~6000 ints/sec */

		/* Flags definitions */
		#define IGC_FLAG_HAS_MSI BIT(0)
		#define IGC_FLAG_QUEUE_PAIRS BIT(3)
		@@ -70,6 +257,7 @@ extern char igc_driver_version[];
		#define IGC_FLAG_HAS_MSIX BIT(13)
		#define IGC_FLAG_VLAN_PROMISC BIT(15)
		#define IGC_FLAG_RX_LEGACY BIT(16)
		#define IGC_FLAG_TSN_QBV_ENABLED BIT(17)

		#define IGC_FLAG_RSS_FIELD_IPV4_UDP BIT(6)
		#define IGC_FLAG_RSS_FIELD_IPV6_UDP BIT(7)
		@@ -78,6 +266,7 @@ extern char igc_driver_version[];
		#define IGC_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
		#define IGC_MRQC_RSS_FIELD_IPV6_UDP 0x00800000

		/* Interrupt defines */
		#define IGC_START_ITR 648 /* ~6000 ints/sec */
		#define IGC_4K_ITR 980
		#define IGC_20K_ITR 196
		@@ -99,13 +288,6 @@ extern char igc_driver_version[];
		#define IGC_MIN_RXD 80
		#define IGC_MAX_RXD 4096

		/* Transmit and receive queues */
		#define IGC_MAX_RX_QUEUES 4
		#define IGC_MAX_TX_QUEUES 4

		#define MAX_Q_VECTORS 8
		#define MAX_STD_JUMBO_FRAME_SIZE 9216

		/* Supported Rx Buffer Sizes */
		#define IGC_RXBUFFER_256 256
		#define IGC_RXBUFFER_2048 2048
		@@ -232,83 +414,6 @@ struct igc_rx_buffer {
		__u16 pagecnt_bias;
		};

		struct igc_tx_queue_stats {
		u64 packets;
		u64 bytes;
		u64 restart_queue;
		u64 restart_queue2;
		};

		struct igc_rx_queue_stats {
		u64 packets;
		u64 bytes;
		u64 drops;
		u64 csum_err;
		u64 alloc_failed;
		};

		struct igc_rx_packet_stats {
		u64 ipv4_packets; /* IPv4 headers processed */
		u64 ipv4e_packets; /* IPv4E headers with extensions processed */
		u64 ipv6_packets; /* IPv6 headers processed */
		u64 ipv6e_packets; /* IPv6E headers with extensions processed */
		u64 tcp_packets; /* TCP headers processed */
		u64 udp_packets; /* UDP headers processed */
		u64 sctp_packets; /* SCTP headers processed */
		u64 nfs_packets; /* NFS headers processe */
		u64 other_packets;
		};

		struct igc_ring_container {
		struct igc_ring ring; / pointer to linked list of rings */
		unsigned int total_bytes; /* total bytes processed this int */
		unsigned int total_packets; /* total packets processed this int */
		u16 work_limit; /* total work allowed per interrupt */
		u8 count; /* total number of rings in vector */
		u8 itr; /* current ITR setting for ring */
		};

		struct igc_ring {
		struct igc_q_vector q_vector; / backlink to q_vector */
		struct net_device netdev; / back pointer to net_device */
		struct device dev; / device for dma mapping */
		union { /* array of buffer info structs */
		struct igc_tx_buffer *tx_buffer_info;
		struct igc_rx_buffer *rx_buffer_info;
		};
		void desc; / descriptor ring memory */
		unsigned long flags; /* ring specific flags */
		void __iomem tail; / pointer to ring tail register */
		dma_addr_t dma; /* phys address of the ring */
		unsigned int size; /* length of desc. ring in bytes */

		u16 count; /* number of desc. in the ring */
		u8 queue_index; /* logical index of the ring*/
		u8 reg_idx; /* physical index of the ring */
		bool launchtime_enable; /* true if LaunchTime is enabled */

		/* everything past this point are written often */
		u16 next_to_clean;
		u16 next_to_use;
		u16 next_to_alloc;

		union {
		/* TX */
		struct {
		struct igc_tx_queue_stats tx_stats;
		struct u64_stats_sync tx_syncp;
		struct u64_stats_sync tx_syncp2;
		};
		/* RX */
		struct {
		struct igc_rx_queue_stats rx_stats;
		struct igc_rx_packet_stats pkt_stats;
		struct u64_stats_sync rx_syncp;
		struct sk_buff *skb;
		};
		};
		} ____cacheline_internodealigned_in_smp;

		struct igc_q_vector {
		struct igc_adapter adapter; / backlink */
		void __iomem *itr_register;
		@@ -329,8 +434,6 @@ struct igc_q_vector {
		struct igc_ring ring[] ____cacheline_internodealigned_in_smp;
		};

		#define MAX_ETYPE_FILTER (4 - 1)

		enum igc_filter_match_flags {
		IGC_FILTER_FLAG_ETHER_TYPE = 0x1,
		IGC_FILTER_FLAG_VLAN_TCI = 0x2,
		@@ -374,108 +477,6 @@ struct igc_mac_addr {

		#define IGC_MAX_RXNFC_FILTERS 16

		/* Board specific private data structure */
		struct igc_adapter {
		struct net_device *netdev;

		unsigned long state;
		unsigned int flags;
		unsigned int num_q_vectors;

		struct msix_entry *msix_entries;

		/* TX */
		u16 tx_work_limit;
		u32 tx_timeout_count;
		int num_tx_queues;
		struct igc_ring *tx_ring[IGC_MAX_TX_QUEUES];

		/* RX */
		int num_rx_queues;
		struct igc_ring *rx_ring[IGC_MAX_RX_QUEUES];

		struct timer_list watchdog_timer;
		struct timer_list dma_err_timer;
		struct timer_list phy_info_timer;

		u32 wol;
		u32 en_mng_pt;
		u16 link_speed;
		u16 link_duplex;

		u8 port_num;

		u8 __iomem *io_addr;
		/* Interrupt Throttle Rate */
		u32 rx_itr_setting;
		u32 tx_itr_setting;

		struct work_struct reset_task;
		struct work_struct watchdog_task;
		struct work_struct dma_err_task;
		bool fc_autoneg;

		u8 tx_timeout_factor;

		int msg_enable;
		u32 max_frame_size;
		u32 min_frame_size;

		/* OS defined structs */
		struct pci_dev *pdev;
		/* lock for statistics */
		spinlock_t stats64_lock;
		struct rtnl_link_stats64 stats64;

		/* structs defined in igc_hw.h */
		struct igc_hw hw;
		struct igc_hw_stats stats;

		struct igc_q_vector *q_vector[MAX_Q_VECTORS];
		u32 eims_enable_mask;
		u32 eims_other;

		u16 tx_ring_count;
		u16 rx_ring_count;

		u32 tx_hwtstamp_timeouts;
		u32 tx_hwtstamp_skipped;
		u32 rx_hwtstamp_cleared;

		u32 rss_queues;
		u32 rss_indir_tbl_init;

		/* RX network flow classification support */
		struct hlist_head nfc_filter_list;
		struct hlist_head cls_flower_list;
		unsigned int nfc_filter_count;

		/* lock for RX network flow classification filter */
		spinlock_t nfc_lock;
		bool etype_bitmap[MAX_ETYPE_FILTER];

		struct igc_mac_addr *mac_table;

		u8 rss_indir_tbl[IGC_RETA_SIZE];

		unsigned long link_check_timeout;
		struct igc_info ei;

		struct ptp_clock *ptp_clock;
		struct ptp_clock_info ptp_caps;
		struct work_struct ptp_tx_work;
		struct sk_buff *ptp_tx_skb;
		struct hwtstamp_config tstamp_config;
		unsigned long ptp_tx_start;
		unsigned long last_rx_ptp_check;
		unsigned long last_rx_timestamp;
		unsigned int ptp_flags;
		/* System time value lock */
		spinlock_t tmreg_lock;
		struct cyclecounter cc;
		struct timecounter tc;
		};

		/* igc_desc_unused - calculate if we have unused descriptors */
		static inline u16 igc_desc_unused(const struct igc_ring *ring)
		{

drivers/net/ethernet/intel/igc/igc_defines.h

+17 −7

Original line number	Diff line number	Diff line
		@@ -44,9 +44,6 @@
		/* Wake Up Packet Memory stores the first 128 bytes of the wake up packet */
		#define IGC_WUPM_BYTES 128

		/* Physical Func Reset Done Indication */
		#define IGC_CTRL_EXT_LINK_MODE_MASK 0x00C00000

		/* Loop limit on how long we wait for auto-negotiation to complete */
		#define COPPER_LINK_UP_LIMIT 10
		#define PHY_AUTO_NEG_LIMIT 45
		@@ -66,8 +63,11 @@
		* (RAR[15]) for our directed address used by controllers with
		* manageability enabled, allowing us room for 15 multicast addresses.
		*/
		#define IGC_RAH_QSEL_MASK 0x000C0000
		#define IGC_RAH_QSEL_SHIFT 18
		#define IGC_RAH_QSEL_ENABLE BIT(28)
		#define IGC_RAH_AV 0x80000000 /* Receive descriptor valid */
		#define IGC_RAH_POOL_1 0x00040000

		#define IGC_RAL_MAC_ADDR_LEN 4
		#define IGC_RAH_MAC_ADDR_LEN 2

		@@ -94,8 +94,6 @@
		#define IGC_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
		#define IGC_CTRL_TFCE 0x10000000 /* Transmit flow control enable */

		#define IGC_CONNSW_AUTOSENSE_EN 0x1

		/* As per the EAS the maximum supported size is 9.5KB (9728 bytes) */
		#define MAX_JUMBO_FRAME_SIZE 0x2600

		@@ -377,6 +375,11 @@
		#define I225_TXPBSIZE_DEFAULT 0x04000014 /* TXPBSIZE default */
		#define IGC_RXPBS_CFG_TS_EN 0x80000000 /* Timestamp in Rx buffer */

		#define IGC_TXPBSIZE_TSN 0x04145145 /* 5k bytes buffer for each queue */

		#define IGC_DTXMXPKTSZ_TSN 0x19 /* 1600 bytes of max TX DMA packet size */
		#define IGC_DTXMXPKTSZ_DEFAULT 0x98 /* 9728-byte Jumbo frames */

		/* Time Sync Interrupt Causes */
		#define IGC_TSICR_SYS_WRAP BIT(0) /* SYSTIM Wrap around. */
		#define IGC_TSICR_TXTS BIT(1) /* Transmit Timestamp. */
		@@ -431,6 +434,14 @@
		#define IGC_TSYNCTXCTL_START_SYNC 0x80000000 /* initiate sync */
		#define IGC_TSYNCTXCTL_TXSYNSIG 0x00000020 /* Sample TX tstamp in PHY sop */

		/* Transmit Scheduling */
		#define IGC_TQAVCTRL_TRANSMIT_MODE_TSN 0x00000001
		#define IGC_TQAVCTRL_ENHANCED_QAV 0x00000008

		#define IGC_TXQCTL_QUEUE_MODE_LAUNCHT 0x00000001
		#define IGC_TXQCTL_STRICT_CYCLE 0x00000002
		#define IGC_TXQCTL_STRICT_END 0x00000004

		/* Receive Checksum Control */
		#define IGC_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */
		#define IGC_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
		@@ -497,7 +508,6 @@
		#define IGC_MDIC_READY 0x10000000
		#define IGC_MDIC_INT_EN 0x20000000
		#define IGC_MDIC_ERROR 0x40000000
		#define IGC_MDIC_DEST 0x80000000

		#define IGC_N0_QUEUE -1

drivers/net/ethernet/intel/igc/igc_ethtool.c

+10 −1

Original line number	Diff line number	Diff line
		@@ -153,7 +153,7 @@ static void igc_get_regs(struct net_device *netdev,

		memset(p, 0, IGC_REGS_LEN * sizeof(u32));

		regs->version = (1u << 24) \| (hw->revision_id << 16) \| hw->device_id;
		regs->version = (2u << 24) \| (hw->revision_id << 16) \| hw->device_id;

		/* General Registers */
		regs_buff[0] = rd32(IGC_CTRL);
		@@ -306,6 +306,15 @@ static void igc_get_regs(struct net_device *netdev,
		regs_buff[164 + i] = rd32(IGC_TDT(i));
		for (i = 0; i < 4; i++)
		regs_buff[168 + i] = rd32(IGC_TXDCTL(i));

		/* XXX: Due to a bug few lines above, RAL and RAH registers are
		* overwritten. To preserve the ABI, we write these registers again in
		* regs_buff.
		*/
		for (i = 0; i < 16; i++)
		regs_buff[172 + i] = rd32(IGC_RAL(i));
		for (i = 0; i < 16; i++)
		regs_buff[188 + i] = rd32(IGC_RAH(i));
		}

		static void igc_get_wol(struct net_device netdev, struct ethtool_wolinfo wol)

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