Commit f892034a authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
Browse files

drm/radeon/kms/igp: fix possible divide by 0 in bandwidth code (v2) 



Some IGP systems specify the system memory clock in the Firmware
table rather than the IGP info table.  Check both and make sure
we have a value system memory clock value.

v2: make sure rs690_pm_info is called on rs780/rs880 as well.

fixes a regression since 07d4190327b02ab3aaad25a2d168f79d92e8f8c2.

Reported-by: default avatarMarkus Trippelsdorf <markus@trippelsdorf.de>
Signed-off-by: default avatarAlex Deucher <alexdeucher@gmail.com>
Tested-by: default avatarMarkus Trippelsdorf <markus@trippelsdorf.de>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 580b4fff

drivers/gpu/drm/radeon/r600.c

+3 −1
Original line number Diff line number Diff line
@@ -1219,8 +1219,10 @@ int r600_mc_init(struct radeon_device *rdev) 
	rdev->mc.visible_vram_size = rdev->mc.aper_size;

	r600_vram_gtt_location(rdev, &rdev->mc);



	if (rdev->flags & RADEON_IS_IGP)

	if (rdev->flags & RADEON_IS_IGP) {

		rs690_pm_info(rdev);

		rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);

	}

	radeon_update_bandwidth_info(rdev);

	return 0;

}

drivers/gpu/drm/radeon/radeon.h

+1 −0
Original line number Diff line number Diff line
@@ -177,6 +177,7 @@ void radeon_pm_resume(struct radeon_device *rdev); 
void radeon_combios_get_power_modes(struct radeon_device *rdev);

void radeon_atombios_get_power_modes(struct radeon_device *rdev);

void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level);

void rs690_pm_info(struct radeon_device *rdev);



/*

 * Fences.

drivers/gpu/drm/radeon/rs690.c

+19 −16
Original line number Diff line number Diff line
@@ -79,7 +79,13 @@ void rs690_pm_info(struct radeon_device *rdev) 
			tmp.full = dfixed_const(100);

			rdev->pm.igp_sideport_mclk.full = dfixed_const(info->info.ulBootUpMemoryClock);

			rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);

			if (info->info.usK8MemoryClock)

				rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock));

			else if (rdev->clock.default_mclk) {

				rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);

				rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);

			} else

				rdev->pm.igp_system_mclk.full = dfixed_const(400);

			rdev->pm.igp_ht_link_clk.full = dfixed_const(le16_to_cpu(info->info.usFSBClock));

			rdev->pm.igp_ht_link_width.full = dfixed_const(info->info.ucHTLinkWidth);

			break;
@@ -87,34 +93,31 @@ void rs690_pm_info(struct radeon_device *rdev) 
			tmp.full = dfixed_const(100);

			rdev->pm.igp_sideport_mclk.full = dfixed_const(info->info_v2.ulBootUpSidePortClock);

			rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);

			if (info->info_v2.ulBootUpUMAClock)

				rdev->pm.igp_system_mclk.full = dfixed_const(info->info_v2.ulBootUpUMAClock);

			else if (rdev->clock.default_mclk)

				rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);

			else

				rdev->pm.igp_system_mclk.full = dfixed_const(66700);

			rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);

			rdev->pm.igp_ht_link_clk.full = dfixed_const(info->info_v2.ulHTLinkFreq);

			rdev->pm.igp_ht_link_clk.full = dfixed_div(rdev->pm.igp_ht_link_clk, tmp);

			rdev->pm.igp_ht_link_width.full = dfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth));

			break;

		default:

			tmp.full = dfixed_const(100);

			/* We assume the slower possible clock ie worst case */

			/* DDR 333Mhz */

			rdev->pm.igp_sideport_mclk.full = dfixed_const(333);

			/* FIXME: system clock ? */

			rdev->pm.igp_system_mclk.full = dfixed_const(100);

			rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);

			rdev->pm.igp_ht_link_clk.full = dfixed_const(200);

			rdev->pm.igp_sideport_mclk.full = dfixed_const(200);

			rdev->pm.igp_system_mclk.full = dfixed_const(200);

			rdev->pm.igp_ht_link_clk.full = dfixed_const(1000);

			rdev->pm.igp_ht_link_width.full = dfixed_const(8);

			DRM_ERROR("No integrated system info for your GPU, using safe default\n");

			break;

		}

	} else {

		tmp.full = dfixed_const(100);

		/* We assume the slower possible clock ie worst case */

		/* DDR 333Mhz */

		rdev->pm.igp_sideport_mclk.full = dfixed_const(333);

		/* FIXME: system clock ? */

		rdev->pm.igp_system_mclk.full = dfixed_const(100);

		rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);

		rdev->pm.igp_ht_link_clk.full = dfixed_const(200);

		rdev->pm.igp_sideport_mclk.full = dfixed_const(200);

		rdev->pm.igp_system_mclk.full = dfixed_const(200);

		rdev->pm.igp_ht_link_clk.full = dfixed_const(1000);

		rdev->pm.igp_ht_link_width.full = dfixed_const(8);

		DRM_ERROR("No integrated system info for your GPU, using safe default\n");

	}

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