Commit f88e2d1f authored by Eric Huang's avatar Eric Huang Committed by Alex Deucher
Browse files

drm/amdgpu: change read of GPU clock counter on Vega10 VF 



Using unified VBIOS has performance drop in sriov environment.
The fix is switching to another register instead.

Signed-off-by: default avatarEric Huang <JinhuiEric.Huang@amd.com>
Reviewed-by: default avatarFelix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 11c61089

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+16 −3
Original line number Original line Diff line number Diff line
@@ -3884,9 +3884,22 @@ static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev) 
	uint64_t clock;

	uint64_t clock;





	mutex_lock(&adev->gfx.gpu_clock_mutex);

	mutex_lock(&adev->gfx.gpu_clock_mutex);

	if (adev->asic_type == CHIP_VEGA10 && amdgpu_sriov_runtime(adev)) {

		uint32_t tmp, lsb, msb, i = 0;

		do {

			if (i != 0)

				udelay(1);

			tmp = RREG32_SOC15(GC, 0, mmRLC_REFCLOCK_TIMESTAMP_MSB);

			lsb = RREG32_SOC15(GC, 0, mmRLC_REFCLOCK_TIMESTAMP_LSB);

			msb = RREG32_SOC15(GC, 0, mmRLC_REFCLOCK_TIMESTAMP_MSB);

			i++;

		} while (unlikely(tmp != msb) && (i < adev->usec_timeout));

		clock = (uint64_t)lsb | ((uint64_t)msb << 32ULL);

	} else {

		WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);

		WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);

		clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |

		clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |

			((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);

			((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);

	}

	mutex_unlock(&adev->gfx.gpu_clock_mutex);

	mutex_unlock(&adev->gfx.gpu_clock_mutex);

	return clock;

	return clock;

}

}

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