Commit f84e63f2 authored by Marek Olšák's avatar Marek Olšák Committed by Alex Deucher
Browse files

drm/amdgpu: fix TC cache flushing 



TC_WB_ACTION must be set according to the docs

Signed-off-by: default avatarMarek Olšák <marek.olsak@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b4eeed59

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

+3 −1
Original line number Diff line number Diff line
@@ -50,9 +50,11 @@ 
 * KMS wrapper.

 * - 3.0.0 - initial driver

 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)

 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same

 *           at the end of IBs.

 */

#define KMS_DRIVER_MAJOR	3

#define KMS_DRIVER_MINOR	1

#define KMS_DRIVER_MINOR	2

#define KMS_DRIVER_PATCHLEVEL	0



int amdgpu_vram_limit = 0;

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

+1 −0
Original line number Diff line number Diff line
@@ -5725,6 +5725,7 @@ static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, 
	amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));

	amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |

				 EOP_TC_ACTION_EN |

				 EOP_TC_WB_ACTION_EN |

				 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |

				 EVENT_INDEX(5)));

	amdgpu_ring_write(ring, addr & 0xfffffffc);

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