Documentation/memory-barriers.txt: Fix ACCESS_ONCE thinko

 (*) On any given CPU, dependent memory accesses will be issued in order, with

 (*) On any given CPU, dependent memory accesses will be issued in order, with

     respect to itself.  This means that for:

     respect to itself.  This means that for:

	WRITE_ONCE(Q, P); smp_read_barrier_depends(); D = READ_ONCE(*Q);

	Q = READ_ONCE(P); smp_read_barrier_depends(); D = READ_ONCE(*Q);

     the CPU will issue the following memory operations:

     the CPU will issue the following memory operations:

     and always in that order.  On most systems, smp_read_barrier_depends()

     and always in that order.  On most systems, smp_read_barrier_depends()

     does nothing, but it is required for DEC Alpha.  The READ_ONCE()

     does nothing, but it is required for DEC Alpha.  The READ_ONCE()

     and WRITE_ONCE() are required to prevent compiler mischief.  Please

     is required to prevent compiler mischief.  Please note that you

     note that you should normally use something like rcu_dereference()

     should normally use something like rcu_dereference() instead of

     instead of open-coding smp_read_barrier_depends().

     open-coding smp_read_barrier_depends().

 (*) Overlapping loads and stores within a particular CPU will appear to be

 (*) Overlapping loads and stores within a particular CPU will appear to be

     ordered within that CPU.  This means that for:

     ordered within that CPU.  This means that for: