Commit f83b7380 authored by Marek Vasut's avatar Marek Vasut Committed by Mark Brown
Browse files

mmc: spi: Add necessary bits into mxs-spi.h 



Add missing register bits and registers into mxs-spi.h .
These will be used by the SPI driver.

Based on previous attempt by:
Fabio Estevam <fabio.estevam@freescale.com>

Signed-off-by: default avatarFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: default avatarMarek Vasut <marex@denx.de>
Acked-by: default avatarChris Ball <cjb@laptop.org>
Acked-by: default avatarShawn Guo <shawn.guo@linaro.org>
Signed-off-by: default avatarMark Brown <broonie@opensource.wolfsonmicro.com>
parent 600a991f

include/linux/spi/mxs-spi.h

+22 −0
Original line number Original line Diff line number Diff line
@@ -30,12 +30,14 @@ 
#define HW_SSP_CTRL0				0x000

#define HW_SSP_CTRL0				0x000

#define  BM_SSP_CTRL0_RUN			(1 << 29)

#define  BM_SSP_CTRL0_RUN			(1 << 29)

#define  BM_SSP_CTRL0_SDIO_IRQ_CHECK		(1 << 28)

#define  BM_SSP_CTRL0_SDIO_IRQ_CHECK		(1 << 28)

#define  BM_SSP_CTRL0_LOCK_CS			(1 << 27)

#define  BM_SSP_CTRL0_IGNORE_CRC		(1 << 26)

#define  BM_SSP_CTRL0_IGNORE_CRC		(1 << 26)

#define  BM_SSP_CTRL0_READ			(1 << 25)

#define  BM_SSP_CTRL0_READ			(1 << 25)

#define  BM_SSP_CTRL0_DATA_XFER			(1 << 24)

#define  BM_SSP_CTRL0_DATA_XFER			(1 << 24)

#define  BP_SSP_CTRL0_BUS_WIDTH			22

#define  BP_SSP_CTRL0_BUS_WIDTH			22

#define  BM_SSP_CTRL0_BUS_WIDTH			(0x3 << 22)

#define  BM_SSP_CTRL0_BUS_WIDTH			(0x3 << 22)

#define  BM_SSP_CTRL0_WAIT_FOR_IRQ		(1 << 21)

#define  BM_SSP_CTRL0_WAIT_FOR_IRQ		(1 << 21)

#define  BM_SSP_CTRL0_WAIT_FOR_CMD		(1 << 20)

#define  BM_SSP_CTRL0_LONG_RESP			(1 << 19)

#define  BM_SSP_CTRL0_LONG_RESP			(1 << 19)

#define  BM_SSP_CTRL0_GET_RESP			(1 << 17)

#define  BM_SSP_CTRL0_GET_RESP			(1 << 17)

#define  BM_SSP_CTRL0_ENABLE			(1 << 16)

#define  BM_SSP_CTRL0_ENABLE			(1 << 16)
@@ -64,8 +66,12 @@ 
#define  BM_SSP_TIMING_TIMEOUT			(0xffff << 16)

#define  BM_SSP_TIMING_TIMEOUT			(0xffff << 16)

#define  BP_SSP_TIMING_CLOCK_DIVIDE		8

#define  BP_SSP_TIMING_CLOCK_DIVIDE		8

#define  BM_SSP_TIMING_CLOCK_DIVIDE		(0xff << 8)

#define  BM_SSP_TIMING_CLOCK_DIVIDE		(0xff << 8)

#define  BF_SSP_TIMING_CLOCK_DIVIDE(v)		\

			(((v) << 8) & BM_SSP_TIMING_CLOCK_DIVIDE)

#define  BP_SSP_TIMING_CLOCK_RATE		0

#define  BP_SSP_TIMING_CLOCK_RATE		0

#define  BM_SSP_TIMING_CLOCK_RATE		0xff

#define  BM_SSP_TIMING_CLOCK_RATE		0xff

#define BF_SSP_TIMING_CLOCK_RATE(v)		\

			(((v) << 0) & BM_SSP_TIMING_CLOCK_RATE)

#define HW_SSP_CTRL1(h)				(ssp_is_old(h) ? 0x060 : 0x080)

#define HW_SSP_CTRL1(h)				(ssp_is_old(h) ? 0x060 : 0x080)

#define  BM_SSP_CTRL1_SDIO_IRQ			(1 << 31)

#define  BM_SSP_CTRL1_SDIO_IRQ			(1 << 31)

#define  BM_SSP_CTRL1_SDIO_IRQ_EN		(1 << 30)

#define  BM_SSP_CTRL1_SDIO_IRQ_EN		(1 << 30)
@@ -84,11 +90,26 @@ 
#define  BM_SSP_CTRL1_FIFO_OVERRUN_IRQ		(1 << 15)

#define  BM_SSP_CTRL1_FIFO_OVERRUN_IRQ		(1 << 15)

#define  BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN	(1 << 14)

#define  BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN	(1 << 14)

#define  BM_SSP_CTRL1_DMA_ENABLE		(1 << 13)

#define  BM_SSP_CTRL1_DMA_ENABLE		(1 << 13)

#define  BM_SSP_CTRL1_PHASE			(1 << 10)

#define  BM_SSP_CTRL1_POLARITY			(1 << 9)

#define  BM_SSP_CTRL1_POLARITY			(1 << 9)

#define  BP_SSP_CTRL1_WORD_LENGTH		4

#define  BP_SSP_CTRL1_WORD_LENGTH		4

#define  BM_SSP_CTRL1_WORD_LENGTH		(0xf << 4)

#define  BM_SSP_CTRL1_WORD_LENGTH		(0xf << 4)

#define  BF_SSP_CTRL1_WORD_LENGTH(v)		\

			(((v) << 4) & BM_SSP_CTRL1_WORD_LENGTH)

#define  BV_SSP_CTRL1_WORD_LENGTH__FOUR_BITS	0x3

#define  BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS	0x7

#define  BV_SSP_CTRL1_WORD_LENGTH__SIXTEEN_BITS	0xF

#define  BP_SSP_CTRL1_SSP_MODE			0

#define  BP_SSP_CTRL1_SSP_MODE			0

#define  BM_SSP_CTRL1_SSP_MODE			0xf

#define  BM_SSP_CTRL1_SSP_MODE			0xf

#define  BF_SSP_CTRL1_SSP_MODE(v)		\

			(((v) << 0) & BM_SSP_CTRL1_SSP_MODE)

#define  BV_SSP_CTRL1_SSP_MODE__SPI		0x0

#define  BV_SSP_CTRL1_SSP_MODE__SSI		0x1

#define  BV_SSP_CTRL1_SSP_MODE__SD_MMC		0x3

#define  BV_SSP_CTRL1_SSP_MODE__MS		0x4



#define HW_SSP_DATA(h)				(ssp_is_old(h) ? 0x070 : 0x090)



#define HW_SSP_SDRESP0(h)			(ssp_is_old(h) ? 0x080 : 0x0a0)

#define HW_SSP_SDRESP0(h)			(ssp_is_old(h) ? 0x080 : 0x0a0)

#define HW_SSP_SDRESP1(h)			(ssp_is_old(h) ? 0x090 : 0x0b0)

#define HW_SSP_SDRESP1(h)			(ssp_is_old(h) ? 0x090 : 0x0b0)

#define HW_SSP_SDRESP2(h)			(ssp_is_old(h) ? 0x0a0 : 0x0c0)

#define HW_SSP_SDRESP2(h)			(ssp_is_old(h) ? 0x0a0 : 0x0c0)
@@ -96,6 +117,7 @@ 
#define HW_SSP_STATUS(h)			(ssp_is_old(h) ? 0x0c0 : 0x100)

#define HW_SSP_STATUS(h)			(ssp_is_old(h) ? 0x0c0 : 0x100)

#define  BM_SSP_STATUS_CARD_DETECT		(1 << 28)

#define  BM_SSP_STATUS_CARD_DETECT		(1 << 28)

#define  BM_SSP_STATUS_SDIO_IRQ			(1 << 17)

#define  BM_SSP_STATUS_SDIO_IRQ			(1 << 17)

#define  BM_SSP_STATUS_FIFO_EMPTY		(1 << 5)





#define BF_SSP(value, field)	(((value) << BP_SSP_##field) & BM_SSP_##field)

#define BF_SSP(value, field)	(((value) << BP_SSP_##field) & BM_SSP_##field)

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