Commit f81c770d authored by Rob Herring's avatar Rob Herring Committed by Lorenzo Pieralisi
Browse files

PCI: dwc: Use DBI accessors instead of own config accessors 

The Designware DBI space contains the root bus bridge config space.
Platforms needing custom {rd,wr}_own_conf functions are also the ones
needing custom {read,write}_dbi ops functions and the access sequences
are the same.

Replace all dw_pcie_{rd,wr}_own_conf() calls with the DBI variants in
preparation to remove dw_pcie_{rd,wr}_own_conf().

Link: https://lore.kernel.org/r/20200821035420.380495-3-robh@kernel.org


Signed-off-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Jingoo Han <jingoohan1@gmail.com>
Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
parent 07e29295

drivers/pci/controller/dwc/pcie-designware-host.c

+19 −36
Original line number Diff line number Diff line
@@ -82,13 +82,13 @@ irqreturn_t dw_handle_msi_irq(struct pcie_port *pp) 
	unsigned long val;

	u32 status, num_ctrls;

	irqreturn_t ret = IRQ_NONE;

	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);



	num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;



	for (i = 0; i < num_ctrls; i++) {

		dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS +

					(i * MSI_REG_CTRL_BLOCK_SIZE),

				    4, &status);

		status = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS +

					   (i * MSI_REG_CTRL_BLOCK_SIZE));

		if (!status)

			continue;
@@ -148,6 +148,7 @@ static int dw_pci_msi_set_affinity(struct irq_data *d, 
static void dw_pci_bottom_mask(struct irq_data *d)

{

	struct pcie_port *pp = irq_data_get_irq_chip_data(d);

	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);

	unsigned int res, bit, ctrl;

	unsigned long flags;
@@ -158,8 +159,7 @@ static void dw_pci_bottom_mask(struct irq_data *d) 
	bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;



	pp->irq_mask[ctrl] |= BIT(bit);

	dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4,

			    pp->irq_mask[ctrl]);

	dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]);



	raw_spin_unlock_irqrestore(&pp->lock, flags);

}
@@ -167,6 +167,7 @@ static void dw_pci_bottom_mask(struct irq_data *d) 
static void dw_pci_bottom_unmask(struct irq_data *d)

{

	struct pcie_port *pp = irq_data_get_irq_chip_data(d);

	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);

	unsigned int res, bit, ctrl;

	unsigned long flags;
@@ -177,8 +178,7 @@ static void dw_pci_bottom_unmask(struct irq_data *d) 
	bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;



	pp->irq_mask[ctrl] &= ~BIT(bit);

	dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4,

			    pp->irq_mask[ctrl]);

	dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]);



	raw_spin_unlock_irqrestore(&pp->lock, flags);

}
@@ -186,13 +186,14 @@ static void dw_pci_bottom_unmask(struct irq_data *d) 
static void dw_pci_bottom_ack(struct irq_data *d)

{

	struct pcie_port *pp  = irq_data_get_irq_chip_data(d);

	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);

	unsigned int res, bit, ctrl;



	ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;

	res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;

	bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;



	dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS + res, 4, BIT(bit));

	dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_STATUS + res, BIT(bit));

}



static struct irq_chip dw_pci_msi_bottom_irq_chip = {
@@ -310,10 +311,8 @@ void dw_pcie_msi_init(struct pcie_port *pp) 
	msi_target = (u64)pp->msi_data;



	/* Program the msi_data */

	dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,

			    lower_32_bits(msi_target));

	dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4,

			    upper_32_bits(msi_target));

	dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_LO, lower_32_bits(msi_target));

	dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target));

}

EXPORT_SYMBOL_GPL(dw_pcie_msi_init);
@@ -327,7 +326,6 @@ int dw_pcie_host_init(struct pcie_port *pp) 
	struct pci_bus *child;

	struct pci_host_bridge *bridge;

	struct resource *cfg_res;

	u32 hdr_type;

	int ret;



	raw_spin_lock_init(&pci->pp.lock);
@@ -453,21 +451,6 @@ int dw_pcie_host_init(struct pcie_port *pp) 
			goto err_free_msi;

	}



	ret = dw_pcie_rd_own_conf(pp, PCI_HEADER_TYPE, 1, &hdr_type);

	if (ret != PCIBIOS_SUCCESSFUL) {

		dev_err(pci->dev, "Failed reading PCI_HEADER_TYPE cfg space reg (ret: 0x%x)\n",

			ret);

		ret = pcibios_err_to_errno(ret);

		goto err_free_msi;

	}

	if (hdr_type != PCI_HEADER_TYPE_BRIDGE) {

		dev_err(pci->dev,

			"PCIe controller is not set to bridge type (hdr_type: 0x%x)!\n",

			hdr_type);

		ret = -EIO;

		goto err_free_msi;

	}



	bridge->sysdata = pp;

	bridge->ops = &dw_pcie_ops;
@@ -638,12 +621,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp) 
		/* Initialize IRQ Status array */

		for (ctrl = 0; ctrl < num_ctrls; ctrl++) {

			pp->irq_mask[ctrl] = ~0;

			dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK +

			dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK +

					    (ctrl * MSI_REG_CTRL_BLOCK_SIZE),

					    4, pp->irq_mask[ctrl]);

			dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE +

					    pp->irq_mask[ctrl]);

			dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_ENABLE +

					    (ctrl * MSI_REG_CTRL_BLOCK_SIZE),

					    4, ~0);

					    ~0);

		}

	}
@@ -685,14 +668,14 @@ void dw_pcie_setup_rc(struct pcie_port *pp) 
						  pp->io_bus_addr, pp->io_size);

	}



	dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);

	dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0);



	/* Program correct class for RC */

	dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);

	dw_pcie_writew_dbi(pci, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI);



	dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);

	val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);

	val |= PORT_LOGIC_SPEED_CHANGE;

	dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);

	dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);



	dw_pcie_dbi_ro_wr_dis(pci);

}

CRA Git | Maintained and supported by SUSTech CRA and CCSE