Commit f81b846d authored Nov 20, 2019 by Lu Baolu Committed by Joerg Roedel Dec 18, 2019

iommu/vt-d: Remove incorrect PSI capability check



The PSI (Page Selective Invalidation) bit in the capability register
is only valid for second-level translation. Intel IOMMU supporting
scalable mode must support page/address selective IOTLB invalidation
for first-level translation. Remove the PSI capability check in SVA
cache invalidation code.

Fixes: 8744daf4 ("iommu/vt-d: Remove global page flush support")
Cc: Jacob Pan <jacob.jun.pan@linux.intel.com>
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>

parent cde9319e

drivers/iommu/intel-svm.c

+1 −5

Original line number	Diff line number	Diff line
		@@ -104,11 +104,7 @@ static void intel_flush_svm_range_dev (struct intel_svm *svm, struct intel_svm_d
		{
		struct qi_desc desc;

		/*
		* Do PASID granu IOTLB invalidation if page selective capability is
		* not available.
		*/
		if (pages == -1 \|\| !cap_pgsel_inv(svm->iommu->cap)) {
		if (pages == -1) {
		desc.qw0 = QI_EIOTLB_PASID(svm->pasid) \|
		QI_EIOTLB_DID(sdev->did) \|
		QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) \|

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