Commit f815bb4e authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'amlogic-dt' of... 

Merge tag 'amlogic-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/dt

ARM: dts: Amlogic updates for v5.1
- more features for Endless EC100 board
- chip temperature sensor support
- fix ethernet pins
- add Mali-450 GPU

* tag 'amlogic-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic

:
  ARM: dts: meson8b: ec100: add the GPIO line names
  ARM: dts: meson8b: ec100: improve the description of the regulators
  ARM: dts: meson8b: ec100: enable the Ethernet PHY interrupt
  ARM: dts: meson8m2: mxiii-plus: add iio-hwmon for the chip temperature
  ARM: dts: meson8b: odroidc1: add iio-hwmon for the chip temperature
  ARM: dts: meson8b: ec100: add iio-hwmon for the chip temperature
  ARM: dts: meson8b: add the temperature calibration data for the SAR ADC
  ARM: dts: meson8: add the temperature calibration data for the SAR ADC
  ARM: dts: meson8m2: use the Meson8m2 specific SAR ADC compatible
  ARM: dts: meson: switch the clock controller to the HHI register area
  ARM: dts: meson8b: fix the Ethernet data line signals in eth_rgmii_pins
  ARM: dts: meson8b: add the Mali-450 MP2 GPU
  ARM: dts: meson8: add the Mali-450 MP6 GPU
  dt-bindings: gpu: mali-utgard: add Amlogic Meson8 and Meson8b compatible
  ARM: dts: meson8b: add the APB bus
  ARM: dts: meson8: add the APB bus
  ARM: dts: meson6: add the APB2 bus

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents e7b98491 99f0619b

Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt

+6 −0
Original line number Diff line number Diff line
@@ -13,6 +13,8 @@ Required properties: 
      + allwinner,sun8i-h3-mali

      + allwinner,sun50i-a64-mali

      + allwinner,sun50i-h5-mali

      + amlogic,meson8-mali

      + amlogic,meson8b-mali

      + amlogic,meson-gxbb-mali

      + amlogic,meson-gxl-mali

      + rockchip,rk3036-mali
@@ -82,6 +84,10 @@ to specify one more vendor-specific compatible, among: 
    Required properties:

      * resets: phandle to the reset line for the GPU



  - amlogic,meson8-mali and amlogic,meson8b-mali

    Required properties:

      * resets: phandle to the reset line for the GPU



  - Rockchip variants:

    Required properties:

      * resets: phandle to the reset line for the GPU

arch/arm/boot/dts/meson.dtsi

+7 −0
Original line number Diff line number Diff line
@@ -73,6 +73,13 @@ 
			#size-cells = <1>;

			ranges = <0x0 0xc1100000 0x200000>;



			hhi: system-controller@4000 {

				compatible = "amlogic,meson-hhi-sysctrl",

					     "simple-mfd",

					     "syscon";

				reg = <0x4000 0x400>;

			};



			assist: assist@7c00 {

				compatible = "amlogic,meson-mx-assist", "syscon";

				reg = <0x7c00 0x200>;

arch/arm/boot/dts/meson6.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -70,6 +70,14 @@ 
		};

	};



	apb2: bus@d0000000 {

		compatible = "simple-bus";

		reg = <0xd0000000 0x40000>;

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x0 0xd0000000 0x40000>;

	};



	xtal: xtal-clk {

		compatible = "fixed-clock";

		clock-frequency = <24000000>;

arch/arm/boot/dts/meson8.dtsi

+82 −7
Original line number Diff line number Diff line
@@ -166,6 +166,32 @@ 
		};

	};



	gpu_opp_table: gpu-opp-table {

		compatible = "operating-points-v2";



		opp-182150000 {

			opp-hz = /bits/ 64 <182150000>;

			opp-microvolt = <1150000>;

		};

		opp-318750000 {

			opp-hz = /bits/ 64 <318750000>;

			opp-microvolt = <1150000>;

		};

		opp-425000000 {

			opp-hz = /bits/ 64 <425000000>;

			opp-microvolt = <1150000>;

		};

		opp-510000000 {

			opp-hz = /bits/ 64 <510000000>;

			opp-microvolt = <1150000>;

		};

		opp-637500000 {

			opp-hz = /bits/ 64 <637500000>;

			opp-microvolt = <1150000>;

			turbo-mode;

		};

	};



	pmu {

		compatible = "arm,cortex-a9-pmu";

		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
@@ -201,6 +227,46 @@ 
			no-map;

		};

	};



	apb: bus@d0000000 {

		compatible = "simple-bus";

		reg = <0xd0000000 0x200000>;

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x0 0xd0000000 0x200000>;



		mali: gpu@c0000 {

			compatible = "amlogic,meson8-mali", "arm,mali-450";

			reg = <0xc0000 0x40000>;

			interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "gp", "gpmmu", "pp", "pmu",

					  "pp0", "ppmmu0", "pp1", "ppmmu1",

					  "pp2", "ppmmu2", "pp4", "ppmmu4",

					  "pp5", "ppmmu5", "pp6", "ppmmu6";

			resets = <&reset RESET_MALI>;

			clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;

			clock-names = "bus", "core";

			operating-points-v2 = <&gpu_opp_table>;

			switch-delay = <0xffff>;

		};

	};

}; /* end of / */



&aobus {
@@ -261,13 +327,6 @@ 
};



&cbus {

	clkc: clock-controller@4000 {

		#clock-cells = <1>;

		#reset-cells = <1>;

		compatible = "amlogic,meson8-clkc";

		reg = <0x8000 0x4>, <0x4000 0x400>;

	};



	reset: reset-controller@4404 {

		compatible = "amlogic,meson8b-reset";

		reg = <0x4404 0x9c>;
@@ -390,6 +449,11 @@ 
	compatible = "amlogic,meson8-efuse";

	clocks = <&clkc CLKID_EFUSE>;

	clock-names = "core";



	temperature_calib: calib@1f4 {

		/* only the upper two bytes are relevant */

		reg = <0x1f4 0x4>;

	};

};



&ethmac {
@@ -402,6 +466,14 @@ 
	status = "okay";

};



&hhi {

	clkc: clock-controller {

		compatible = "amlogic,meson8-clkc";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};

};



&hwrng {

	compatible = "amlogic,meson8-rng", "amlogic,meson-rng";

	clocks = <&clkc CLKID_RNG0>;
@@ -469,6 +541,9 @@ 
	clocks = <&clkc CLKID_XTAL>,

		<&clkc CLKID_SAR_ADC>;

	clock-names = "clkin", "core";

	amlogic,hhi-sysctrl = <&hhi>;

	nvmem-cells = <&temperature_calib>;

	nvmem-cell-names = "temperature_calib";

};



&sdio {

arch/arm/boot/dts/meson8b-ec100.dts

+127 −0
Original line number Diff line number Diff line
@@ -65,6 +65,11 @@ 
		timeout-ms = <20000>;

	};



	iio-hwmon {

		compatible = "iio-hwmon";

		io-channels = <&saradc 8>;

	};



	leds {

		compatible = "gpio-leds";
@@ -84,6 +89,9 @@ 
	};



	usb_vbus: regulator-usb-vbus {

		/*

		 * Silergy SY6288CCAC-GP 2A Power Distribution Switch.

		 */

		compatible = "regulator-fixed";



		regulator-name = "USB_VBUS";
@@ -91,11 +99,20 @@ 
		regulator-min-microvolt = <5000000>;

		regulator-max-microvolt = <5000000>;



		vin-supply = <&vcc_5v>;



		/*

		 * signal name from the schematics: USB_PWR_EN

		 */

		gpio = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>;

		enable-active-high;

	};



	vcc_5v: regulator-vcc5v {

		/*

		 * supplied by the main power input which called PWR_5V_STB

		 * in the schematics

		 */

		compatible = "regulator-fixed";



		regulator-name = "VCC5V";
@@ -103,6 +120,9 @@ 
		regulator-min-microvolt = <5000000>;

		regulator-max-microvolt = <5000000>;



		/*

		 * signal name from the schematics: 3V3_5V_EN

		 */

		gpio = <&gpio GPIODV_29 GPIO_ACTIVE_LOW>;



		regulator-boot-on;
@@ -110,12 +130,18 @@ 
	};



	vcck: regulator-vcck {

		/*

		 * Silergy SY8089AAC-GP 2A continuous, 3A peak, 1MHz

		 * Synchronous Step Down Regulator.

		 */

		compatible = "pwm-regulator";



		regulator-name = "VCCK";

		regulator-min-microvolt = <860000>;

		regulator-max-microvolt = <1140000>;



		vin-supply = <&vcc_5v>;



		pwms = <&pwm_cd 0 1148 0>;

		pwm-dutycycle-range = <100 0>;
@@ -124,19 +150,66 @@ 
	};



	vcc_1v8: regulator-vcc1v8 {

		/*

		 * ABLIC S-1339D18-M5001-GP

		 */

		compatible = "regulator-fixed";



		regulator-name = "VCC1V8";

		regulator-min-microvolt = <1800000>;

		regulator-max-microvolt = <1800000>;



		vin-supply = <&vcc_3v3>;

	};



	vcc_3v3: regulator-vcc3v3 {

		/*

		 * Silergy SY8089AAC-GP 2A continuous, 3A peak, 1MHz

		 * Synchronous Step Down Regulator. Also called

		 * VDDIO_AO3.3V in the schematics.

		 */

		compatible = "regulator-fixed";



		regulator-name = "VCC3V3";

		regulator-min-microvolt = <3300000>;

		regulator-max-microvolt = <3300000>;



		vin-supply = <&vcc_5v>;

	};



	vcc_ddr3: regulator-vcc-ddr3 {

		/*

		 * Silergy SY8089AAC-GP 2A continuous, 3A peak, 1MHz

		 * Synchronous Step Down Regulator. Also called

		 * DDR3_1.5V in the schematics.

		 */

		compatible = "regulator-fixed";



		regulator-name = "VCC_DDR3_1V5";

		regulator-min-microvolt = <1500000>;

		regulator-max-microvolt = <1500000>;



		vin-supply = <&vcc_5v>;



		regulator-boot-on;

		regulator-always-on;

	};



	vcc_rtc: regulator-vcc-rtc {

		/*

		 * Global Mixed-mode Technology Inc. G918T12U-GP

		 */

		compatible = "regulator-fixed";



		regulator-name = "VCC_RTC";

		regulator-min-microvolt = <900000>;

		regulator-max-microvolt = <900000>;



		/*

		 * When the board is powered then the input is VCC3V3,

		 * otherwise power is taken from the coin cell battery.

		 */

		vin-supply = <&vcc_3v3>;

	};

};
@@ -165,6 +238,10 @@ 
		eth_phy0: ethernet-phy@0 {

			/* IC Plus IP101A/G (0x02430c54) */

			reg = <0>;

			icplus,select-interrupt;

			interrupt-parent = <&gpio_intc>;

			/* GPIOH_3 */

			interrupts = <17 IRQ_TYPE_LEVEL_LOW>;

		};

	};

};
@@ -213,6 +290,56 @@ 
	};

};



&gpio_ao {

	gpio-line-names = "Linux_TX", "Linux_RX",

			  "SLP_S5_N", "USB2_OC_FLAG#",

			  "HUB_RST", "USB_PWR_EN",

			  "I2S_IN", "SLP_S1_N",

			  "TCK", "TMS", "TDI", "TDO",

			  "HDMI_CEC", "5640_IRQ",

			  "MUTE", "S805_TEST#";

};



&gpio {

	gpio-line-names = /* Bank GPIOX */

			  "WIFI_SD_D0", "WIFI_SD_D1", "WIFI_SD_D2",

			  "WIFI_SD_D3", "BTPCM_DOUT", "BTPCM_DIN",

			  "BTPCM_SYNC", "BTPCM_CLK", "WIFI_SD_CLK",

			  "WIFI_SD_CMD", "WIFI_32K", "WIFI_PWREN",

			  "UART_B_TX", "UART_B_RX", "UART_B_CTS_N",

			  "UART_B_RTS_N", "BT_EN", "WIFI_WAKE_HOST",

			  /* Bank GPIOY */

			  "", "", "", "", "", "", "", "", "", "",

			  "", "",

			  /* Bank GPIODV */

			  "VCCK_PWM_C", "I2C_SDA_A", "I2C_SCL_A",

			  "I2C_SDA_B", "I2C_SCL_B", "VDDEE_PWM_D",

			  "VDDEE_PWM 3V3_5V_EN",

			  /* Bank GPIOH */

			  "HDMI_HPD", "HDMI_I2C_SDA", "HDMI_I2C_SCL",

			  "RMII_IRQ", "RMII_RST#", "RMII_TXD1",

			  "RMII_TXD0", "AV_select_1", "AV_select_2",

			  "MCU_Control_S",

			  /* Bank CARD */

			  "SD_D1_B", "SD_D0_B", "SD_CLK_8726MX",

			  "SD_CMD_8726MX", "SD_D3_B", "SD_D2_B",

			  "CARD_EN_DET (CARD_DET)",

			  /* Bank BOOT */

			  "NAND_D0 (EMMC)", "NAND_D1 (EMMC)",

			  "NAND_D2 (EMMC)", "NAND_D3 (EMMC)",

			  "NAND_D4 (EMMC)", "NAND_D5 (EMMC)",

			  "NAND_D6 (EMMC)", "NAND_D7 (EMMC)",

			  "NAND_CS1 (EMMC)", "NAND_CS2 iNAND_RS1 (EMMC)",

			  "NAND_nR/B iNAND_CMD (EMMC)", "NAND_ALE (EMMC)",

			  "NAND_CLE (EMMC)", "nRE_S1 NAND_nRE (EMMC)",

			  "nWE_S1 NAND_nWE (EMMC)",  "", "", "SPI_CS",

			  /* Bank DIF */

			  "RMII_RXD1", "RMII_RXD0", "RMII_CRS_DV",

			  "RMII_50M_IN", "GPIODIF_4", "GPIODIF_5",

			  "RMII_TXEN", "CPUETH_25MOUT", "RMII_MDC",

			  "RMII_MDIO";

};



&pwm_cd {

	status = "okay";

	pinctrl-0 = <&pwm_c1_pins>;

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