Commit f80a71b0 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-next-2018-08-17' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "First round of fixes for -rc1. I'll follow this up with the msm new hw
  support pull request.

  This just has three sets of fixes, some for msm before the new hw, a
  bunch of AMD fixes (includiing some required firmware changes for new
  hw), and a set of i915 (+gvt) fixes"

* tag 'drm-next-2018-08-17' of git://anongit.freedesktop.org/drm/drm: (30 commits)
  drm/amdgpu: Use kvmalloc for allocating UVD/VCE/VCN BO backup memory
  drm/i915: set DP Main Stream Attribute for color range on DDI platforms
  drm/i915/selftests: Hold rpm for unparking
  drm/i915: Restore user forcewake domains across suspend
  drm/i915: Unmask user interrupts writes into HWSP on snb/ivb/vlv/hsw
  drm/i915/gvt: fix memory leak in intel_vgpu_ioctl()
  drm/i915/gvt: Off by one in intel_vgpu_write_fence()
  drm/i915/kvmgt: Fix potential Spectre v1
  drm/i915/gvt: return error on cmd access
  drm/i915/gvt: initialize dmabuf mutex in vgpu_create
  drm/i915/gvt: fix cleanup sequence in intel_gvt_clean_device
  drm/amd/display: Guard against null crtc in CRC IRQ
  drm/amd/display: Pass connector id when executing VBIOS CT
  drm/amd/display: Check if clock source in use before disabling
  drm/amd/display: Allow clock sharing b/w HDMI and DVI
  drm/amd/display: Fix warning observed in mode change on Vega
  drm/amd/display: fix single link DVI has no display
  drm/amdgpu/vce: VCE entity initialization relies on ring initializtion
  drm/amdgpu/uvd: UVD entity initialization relys on ring initialization
  drm/amdgpu:add VCN booting with firmware loaded by PSP
  ...
parents edb0a200 0258d7a5

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

+5 −0
Original line number Diff line number Diff line
@@ -131,6 +131,11 @@ psp_cmd_submit_buf(struct psp_context *psp, 
		msleep(1);

	}



	if (ucode) {

		ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;

		ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;

	}



	return ret;

}

drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h

+4 −0
Original line number Diff line number Diff line
@@ -194,6 +194,7 @@ enum AMDGPU_UCODE_ID { 
	AMDGPU_UCODE_ID_SMC,

	AMDGPU_UCODE_ID_UVD,

	AMDGPU_UCODE_ID_VCE,

	AMDGPU_UCODE_ID_VCN,

	AMDGPU_UCODE_ID_MAXIMUM,

};
@@ -226,6 +227,9 @@ struct amdgpu_firmware_info { 
	void *kaddr;

	/* ucode_size_bytes */

	uint32_t ucode_size;

	/* starting tmr mc address */

	uint32_t tmr_mc_addr_lo;

	uint32_t tmr_mc_addr_hi;

};



void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr);

drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c

+26 −12
Original line number Diff line number Diff line
@@ -122,8 +122,6 @@ static void amdgpu_uvd_idle_work_handler(struct work_struct *work); 


int amdgpu_uvd_sw_init(struct amdgpu_device *adev)

{

	struct amdgpu_ring *ring;

	struct drm_sched_rq *rq;

	unsigned long bo_size;

	const char *fw_name;

	const struct common_firmware_header *hdr;
@@ -266,13 +264,6 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev) 
		}

	}



	ring = &adev->uvd.inst[0].ring;

	rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];

	r = drm_sched_entity_init(&adev->uvd.entity, &rq, 1, NULL);

	if (r) {

		DRM_ERROR("Failed setting up UVD kernel entity.\n");

		return r;

	}

	for (i = 0; i < adev->uvd.max_handles; ++i) {

		atomic_set(&adev->uvd.handles[i], 0);

		adev->uvd.filp[i] = NULL;
@@ -311,7 +302,7 @@ int amdgpu_uvd_sw_fini(struct amdgpu_device *adev) 
	for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {

		if (adev->uvd.harvest_config & (1 << j))

			continue;

		kfree(adev->uvd.inst[j].saved_bo);

		kvfree(adev->uvd.inst[j].saved_bo);



		amdgpu_bo_free_kernel(&adev->uvd.inst[j].vcpu_bo,

				      &adev->uvd.inst[j].gpu_addr,
@@ -327,6 +318,29 @@ int amdgpu_uvd_sw_fini(struct amdgpu_device *adev) 
	return 0;

}



/**

 * amdgpu_uvd_entity_init - init entity

 *

 * @adev: amdgpu_device pointer

 *

 */

int amdgpu_uvd_entity_init(struct amdgpu_device *adev)

{

	struct amdgpu_ring *ring;

	struct drm_sched_rq *rq;

	int r;



	ring = &adev->uvd.inst[0].ring;

	rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];

	r = drm_sched_entity_init(&adev->uvd.entity, &rq, 1, NULL);

	if (r) {

		DRM_ERROR("Failed setting up UVD kernel entity.\n");

		return r;

	}



	return 0;

}



int amdgpu_uvd_suspend(struct amdgpu_device *adev)

{

	unsigned size;
@@ -354,7 +368,7 @@ int amdgpu_uvd_suspend(struct amdgpu_device *adev) 
		size = amdgpu_bo_size(adev->uvd.inst[j].vcpu_bo);

		ptr = adev->uvd.inst[j].cpu_addr;



		adev->uvd.inst[j].saved_bo = kmalloc(size, GFP_KERNEL);

		adev->uvd.inst[j].saved_bo = kvmalloc(size, GFP_KERNEL);

		if (!adev->uvd.inst[j].saved_bo)

			return -ENOMEM;
@@ -380,7 +394,7 @@ int amdgpu_uvd_resume(struct amdgpu_device *adev) 


		if (adev->uvd.inst[i].saved_bo != NULL) {

			memcpy_toio(ptr, adev->uvd.inst[i].saved_bo, size);

			kfree(adev->uvd.inst[i].saved_bo);

			kvfree(adev->uvd.inst[i].saved_bo);

			adev->uvd.inst[i].saved_bo = NULL;

		} else {

			const struct common_firmware_header *hdr;

drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h

+1 −0
Original line number Diff line number Diff line
@@ -69,6 +69,7 @@ struct amdgpu_uvd { 


int amdgpu_uvd_sw_init(struct amdgpu_device *adev);

int amdgpu_uvd_sw_fini(struct amdgpu_device *adev);

int amdgpu_uvd_entity_init(struct amdgpu_device *adev);

int amdgpu_uvd_suspend(struct amdgpu_device *adev);

int amdgpu_uvd_resume(struct amdgpu_device *adev);

int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,

drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c

+23 −10
Original line number Diff line number Diff line
@@ -90,8 +90,6 @@ static void amdgpu_vce_idle_work_handler(struct work_struct *work); 
 */

int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size)

{

	struct amdgpu_ring *ring;

	struct drm_sched_rq *rq;

	const char *fw_name;

	const struct common_firmware_header *hdr;

	unsigned ucode_version, version_major, version_minor, binary_id;
@@ -188,14 +186,6 @@ int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size) 
		return r;

	}



	ring = &adev->vce.ring[0];

	rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];

	r = drm_sched_entity_init(&adev->vce.entity, &rq, 1, NULL);

	if (r != 0) {

		DRM_ERROR("Failed setting up VCE run queue.\n");

		return r;

	}



	for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {

		atomic_set(&adev->vce.handles[i], 0);

		adev->vce.filp[i] = NULL;
@@ -235,6 +225,29 @@ int amdgpu_vce_sw_fini(struct amdgpu_device *adev) 
	return 0;

}



/**

 * amdgpu_vce_entity_init - init entity

 *

 * @adev: amdgpu_device pointer

 *

 */

int amdgpu_vce_entity_init(struct amdgpu_device *adev)

{

	struct amdgpu_ring *ring;

	struct drm_sched_rq *rq;

	int r;



	ring = &adev->vce.ring[0];

	rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];

	r = drm_sched_entity_init(&adev->vce.entity, &rq, 1, NULL);

	if (r != 0) {

		DRM_ERROR("Failed setting up VCE run queue.\n");

		return r;

	}



	return 0;

}



/**

 * amdgpu_vce_suspend - unpin VCE fw memory

 *

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