Commit f7fe9334 authored by David S. Miller's avatar David S. Miller
Browse files

sparc64: Remove 4MB and 512K base page size options. 



Adrian Bunk reported that enabling 4MB page size breaks the build.
The problem is that MAX_ORDER combined with the page shift exceeds the
SECTION_SIZE_BITS we use in asm-sparc64/sparsemem.h

There are several ways I suppose we could work around this.  For one
we could define a CONFIG_FORCE_MAX_ZONEORDER to decrease MAX_ORDER in
these higher page size cases.

But I also know that these page size cases are broken wrt. TLB miss
handling especially on pre-hypervisor systems, and there isn't an easy
way to fix that.

These options were meant to be fun experimental hacks anyways, and
only 8K and 64K make any sense to support.

So remove 512K and 4M base page size support.  Of course, we still
support these page sizes for huge pages.

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent d172ad18

arch/sparc64/Kconfig

+1 −10
Original line number Diff line number Diff line
@@ -98,19 +98,11 @@ config SPARC64_PAGE_SIZE_8KB 
	  8KB and 64KB work quite well, since SPARC ELF sections

	  provide for up to 64KB alignment.



	  Therefore, 512KB and 4MB are for expert hackers only.



	  If you don't know what to do, choose 8KB.



config SPARC64_PAGE_SIZE_64KB

	bool "64KB"



config SPARC64_PAGE_SIZE_512KB

	bool "512KB"



config SPARC64_PAGE_SIZE_4MB

	bool "4MB"



endchoice



config SECCOMP
@@ -226,11 +218,10 @@ config HUGETLB_PAGE_SIZE_4MB 
	bool "4MB"



config HUGETLB_PAGE_SIZE_512K

	depends on !SPARC64_PAGE_SIZE_4MB && !SPARC64_PAGE_SIZE_512KB

	bool "512K"



config HUGETLB_PAGE_SIZE_64K

	depends on !SPARC64_PAGE_SIZE_4MB && !SPARC64_PAGE_SIZE_512KB && !SPARC64_PAGE_SIZE_64KB

	depends on !SPARC64_PAGE_SIZE_64KB

	bool "64K"



endchoice

arch/sparc64/lib/copy_page.S

+3 −3
Original line number Diff line number Diff line
@@ -25,9 +25,9 @@ 


#define	DCACHE_SIZE	(PAGE_SIZE * 2)



#if (PAGE_SHIFT == 13) || (PAGE_SHIFT == 19)

#if (PAGE_SHIFT == 13)

#define PAGE_SIZE_REM	0x80

#elif (PAGE_SHIFT == 16) || (PAGE_SHIFT == 22)

#elif (PAGE_SHIFT == 16)

#define PAGE_SIZE_REM	0x100

#else

#error Wrong PAGE_SHIFT specified
@@ -198,7 +198,7 @@ cheetah_copy_page_insn: 
	cmp		%o2, PAGE_SIZE_REM

	bne,pt		%xcc, 1b

	 add		%o0, 0x40, %o0

#if (PAGE_SHIFT == 16) || (PAGE_SHIFT == 22)

#if (PAGE_SHIFT == 16)

	TOUCH(f0, f2, f4, f6, f8, f10, f12, f14)

	ldda		[%o1] ASI_BLK_P, %f32

	stda		%f48, [%o0] %asi

arch/sparc64/mm/tsb.c

+0 −6
Original line number Diff line number Diff line
@@ -96,12 +96,6 @@ void flush_tsb_user(struct mmu_gather *mp) 
#elif defined(CONFIG_SPARC64_PAGE_SIZE_64KB)

#define HV_PGSZ_IDX_BASE	HV_PGSZ_IDX_64K

#define HV_PGSZ_MASK_BASE	HV_PGSZ_MASK_64K

#elif defined(CONFIG_SPARC64_PAGE_SIZE_512KB)

#define HV_PGSZ_IDX_BASE	HV_PGSZ_IDX_512K

#define HV_PGSZ_MASK_BASE	HV_PGSZ_MASK_512K

#elif defined(CONFIG_SPARC64_PAGE_SIZE_4MB)

#define HV_PGSZ_IDX_BASE	HV_PGSZ_IDX_4MB

#define HV_PGSZ_MASK_BASE	HV_PGSZ_MASK_4MB

#else

#error Broken base page size setting...

#endif

include/asm-sparc/mmu_64.h

+0 −4
Original line number Diff line number Diff line
@@ -34,10 +34,6 @@ 
#define CTX_PGSZ_BASE	CTX_PGSZ_8KB

#elif defined(CONFIG_SPARC64_PAGE_SIZE_64KB)

#define CTX_PGSZ_BASE	CTX_PGSZ_64KB

#elif defined(CONFIG_SPARC64_PAGE_SIZE_512KB)

#define CTX_PGSZ_BASE	CTX_PGSZ_512KB

#elif defined(CONFIG_SPARC64_PAGE_SIZE_4MB)

#define CTX_PGSZ_BASE	CTX_PGSZ_4MB

#else

#error No page size specified in kernel configuration

#endif

include/asm-sparc/page_64.h

+0 −4
Original line number Diff line number Diff line
@@ -7,10 +7,6 @@ 
#define PAGE_SHIFT   13

#elif defined(CONFIG_SPARC64_PAGE_SIZE_64KB)

#define PAGE_SHIFT   16

#elif defined(CONFIG_SPARC64_PAGE_SIZE_512KB)

#define PAGE_SHIFT   19

#elif defined(CONFIG_SPARC64_PAGE_SIZE_4MB)

#define PAGE_SHIFT   22

#else

#error No page size specified in kernel configuration

#endif

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