Commit f7f842cc authored by Fabien Parent's avatar Fabien Parent Committed by Joerg Roedel
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dt-bindings: iommu: Add binding for MediaTek MT8167 IOMMU 



This commit adds IOMMU binding documentation and larb port definitions
for the MT8167 SoC.

Signed-off-by: default avatarFabien Parent <fparent@baylibre.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20200907101649.1573134-1-fparent@baylibre.com


Signed-off-by: default avatarJoerg Roedel <jroedel@suse.de>
parent c2c59456

Documentation/devicetree/bindings/iommu/mediatek,iommu.txt

+2 −0
Original line number Diff line number Diff line
@@ -61,6 +61,7 @@ Required properties: 
	"mediatek,mt6779-m4u" for mt6779 which uses generation two m4u HW.

	"mediatek,mt7623-m4u", "mediatek,mt2701-m4u" for mt7623 which uses

						     generation one m4u HW.

	"mediatek,mt8167-m4u" for mt8167 which uses generation two m4u HW.

	"mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW.

	"mediatek,mt8183-m4u" for mt8183 which uses generation two m4u HW.

- reg : m4u register base and size.
@@ -80,6 +81,7 @@ Required properties: 
	dt-binding/memory/mt2701-larb-port.h for mt2701, mt7623

	dt-binding/memory/mt2712-larb-port.h for mt2712,

	dt-binding/memory/mt6779-larb-port.h for mt6779,

	dt-binding/memory/mt8167-larb-port.h for mt8167,

	dt-binding/memory/mt8173-larb-port.h for mt8173, and

	dt-binding/memory/mt8183-larb-port.h for mt8183.

include/dt-bindings/memory/mt8167-larb-port.h

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+51 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/*

 * Copyright (c) 2020 MediaTek Inc.

 * Copyright (c) 2020 BayLibre, SAS

 * Author: Honghui Zhang <honghui.zhang@mediatek.com>

 * Author: Fabien Parent <fparent@baylibre.com>

 */

#ifndef __DTS_IOMMU_PORT_MT8167_H

#define __DTS_IOMMU_PORT_MT8167_H



#define MTK_M4U_ID(larb, port)		(((larb) << 5) | (port))



#define M4U_LARB0_ID			0

#define M4U_LARB1_ID			1

#define M4U_LARB2_ID			2



/* larb0 */

#define M4U_PORT_DISP_OVL0		MTK_M4U_ID(M4U_LARB0_ID, 0)

#define M4U_PORT_DISP_RDMA0		MTK_M4U_ID(M4U_LARB0_ID, 1)

#define M4U_PORT_DISP_WDMA0		MTK_M4U_ID(M4U_LARB0_ID, 2)

#define M4U_PORT_DISP_RDMA1		MTK_M4U_ID(M4U_LARB0_ID, 3)

#define M4U_PORT_MDP_RDMA		MTK_M4U_ID(M4U_LARB0_ID, 4)

#define M4U_PORT_MDP_WDMA		MTK_M4U_ID(M4U_LARB0_ID, 5)

#define M4U_PORT_MDP_WROT		MTK_M4U_ID(M4U_LARB0_ID, 6)

#define M4U_PORT_DISP_FAKE		MTK_M4U_ID(M4U_LARB0_ID, 7)



/* larb1*/

#define M4U_PORT_CAM_IMGO		MTK_M4U_ID(M4U_LARB1_ID, 0)

#define M4U_PORT_CAM_IMG2O		MTK_M4U_ID(M4U_LARB1_ID, 1)

#define M4U_PORT_CAM_LSCI		MTK_M4U_ID(M4U_LARB1_ID, 2)

#define M4U_PORT_CAM_ESFKO		MTK_M4U_ID(M4U_LARB1_ID, 3)

#define M4U_PORT_CAM_AAO		MTK_M4U_ID(M4U_LARB1_ID, 4)

#define M4U_PORT_VENC_REC		MTK_M4U_ID(M4U_LARB1_ID, 5)

#define M4U_PORT_VENC_BSDMA		MTK_M4U_ID(M4U_LARB1_ID, 6)

#define M4U_PORT_VENC_RD_COMV		MTK_M4U_ID(M4U_LARB1_ID, 7)

#define M4U_PORT_CAM_IMGI		MTK_M4U_ID(M4U_LARB1_ID, 8)

#define M4U_PORT_VENC_CUR_LUMA		MTK_M4U_ID(M4U_LARB1_ID, 9)

#define M4U_PORT_VENC_CUR_CHROMA	MTK_M4U_ID(M4U_LARB1_ID, 10)

#define M4U_PORT_VENC_REF_LUMA		MTK_M4U_ID(M4U_LARB1_ID, 11)

#define M4U_PORT_VENC_REF_CHROMA	MTK_M4U_ID(M4U_LARB1_ID, 12)



/* larb2*/

#define M4U_PORT_HW_VDEC_MC_EXT		MTK_M4U_ID(M4U_LARB2_ID, 0)

#define M4U_PORT_HW_VDEC_PP_EXT		MTK_M4U_ID(M4U_LARB2_ID, 1)

#define M4U_PORT_HW_VDEC_VLD_EXT	MTK_M4U_ID(M4U_LARB2_ID, 2)

#define M4U_PORT_HW_VDEC_AVC_MV_EXT	MTK_M4U_ID(M4U_LARB2_ID, 3)

#define M4U_PORT_HW_VDEC_PRED_RD_EXT	MTK_M4U_ID(M4U_LARB2_ID, 4)

#define M4U_PORT_HW_VDEC_PRED_WR_EXT	MTK_M4U_ID(M4U_LARB2_ID, 5)

#define M4U_PORT_HW_VDEC_PPWRAP_EXT	MTK_M4U_ID(M4U_LARB2_ID, 6)



#endif

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