Commit f7f17a67 authored by Dmitri Vorobiev's avatar Dmitri Vorobiev Committed by Ingo Molnar
Browse files

x86: remove NexGen support 

It is claimed that NexGen CPUs were never shipped:

   http://lkml.org/lkml/2008/4/20/179



Also, the kernel support for these chips has been broken for
a long time, the code intended to support NexGen thereby being
essentially dead.

As an outcome of the discussion that can be found using the URL
above, this patch removes the NexGen support altogether.

The changes in this patch survived a defconfig build for i386, a
couple of successful randconfig builds, as well as a runtime test,
which consisted in booting a 32-bit x86 box up to the shell prompt.

Signed-off-by: default avatarDmitri Vorobiev <dmitri.vorobiev@gmail.com>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent a2b4bd9c

arch/x86/Kconfig.cpu

+2 −2
Original line number Diff line number Diff line
@@ -21,8 +21,8 @@ config M386 


	  Here are the settings recommended for greatest speed:

	  - "386" for the AMD/Cyrix/Intel 386DX/DXL/SL/SLC/SX, Cyrix/TI

	  486DLC/DLC2, UMC 486SX-S and NexGen Nx586.  Only "386" kernels

	  will run on a 386 class machine.

	  486DLC/DLC2, and UMC 486SX-S.  Only "386" kernels will run on a 386

	  class machine.

	  - "486" for the AMD/Cyrix/IBM/Intel 486DX/DX2/DX4 or

	  SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5D or U5S.

	  - "586" for generic Pentium CPUs lacking the TSC

arch/x86/kernel/cpu/Makefile

+0 −1
Original line number Diff line number Diff line
@@ -11,7 +11,6 @@ obj-$(CONFIG_X86_32) += cyrix.o 
obj-$(CONFIG_X86_32)	+= centaur.o

obj-$(CONFIG_X86_32)	+= transmeta.o

obj-$(CONFIG_X86_32)	+= intel.o

obj-$(CONFIG_X86_32)	+= nexgen.o

obj-$(CONFIG_X86_32)	+= umc.o



obj-$(CONFIG_X86_MCE)	+= mcheck/

arch/x86/kernel/cpu/nexgen.c

deleted100644 → 0
+0 −59
Original line number Diff line number Diff line 
#include <linux/kernel.h>

#include <linux/init.h>

#include <linux/string.h>

#include <asm/processor.h>



#include "cpu.h"



/*

 *	Detect a NexGen CPU running without BIOS hypercode new enough

 *	to have CPUID. (Thanks to Herbert Oppmann)

 */



static int __cpuinit deep_magic_nexgen_probe(void)

{

	int ret;



	__asm__ __volatile__ (

		"	movw	$0x5555, %%ax\n"

		"	xorw	%%dx,%%dx\n"

		"	movw	$2, %%cx\n"

		"	divw	%%cx\n"

		"	movl	$0, %%eax\n"

		"	jnz	1f\n"

		"	movl	$1, %%eax\n"

		"1:\n"

		: "=a" (ret) : : "cx", "dx");

	return  ret;

}



static void __cpuinit init_nexgen(struct cpuinfo_x86 *c)

{

	c->x86_cache_size = 256; /* A few had 1 MB... */

}



static void __cpuinit nexgen_identify(struct cpuinfo_x86 *c)

{

	/* Detect NexGen with old hypercode */

	if (deep_magic_nexgen_probe())

		strcpy(c->x86_vendor_id, "NexGenDriven");

}



static struct cpu_dev nexgen_cpu_dev __cpuinitdata = {

	.c_vendor	= "Nexgen",

	.c_ident	= { "NexGenDriven" },

	.c_models = {

			{ .vendor = X86_VENDOR_NEXGEN,

			  .family = 5,

			  .model_names = { [1] = "Nx586" }

			},

	},

	.c_init		= init_nexgen,

	.c_identify	= nexgen_identify,

};



int __init nexgen_init_cpu(void)

{

	cpu_devs[X86_VENDOR_NEXGEN] = &nexgen_cpu_dev;

	return 0;

}

arch/x86/mm/init_32.c

+3 −3
Original line number Diff line number Diff line
@@ -566,9 +566,9 @@ void __init paging_init(void) 


/*

 * Test if the WP bit works in supervisor mode. It isn't supported on 386's

 * and also on some strange 486's (NexGen etc.). All 586+'s are OK. This

 * used to involve black magic jumps to work around some nasty CPU bugs,

 * but fortunately the switch to using exceptions got rid of all that.

 * and also on some strange 486's. All 586+'s are OK. This used to involve

 * black magic jumps to work around some nasty CPU bugs, but fortunately the

 * switch to using exceptions got rid of all that.

 */

static void __init test_wp_bit(void)

{

include/asm-x86/processor.h

+0 −1
Original line number Diff line number Diff line
@@ -118,7 +118,6 @@ struct cpuinfo_x86 { 
#define X86_VENDOR_CYRIX	1

#define X86_VENDOR_AMD		2

#define X86_VENDOR_UMC		3

#define X86_VENDOR_NEXGEN	4

#define X86_VENDOR_CENTAUR	5

#define X86_VENDOR_TRANSMETA	7

#define X86_VENDOR_NSC		8

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